DW1000 User Manual
© Decawave Ltd 2017
Version 2.12
Page 48 of 242
5
Media Access Control (MAC) hardware features
This section describes the features for media access control (MAC) that have been implemented in the
DW1000.
5.1 Cyclic redundancy check
The DW1000 includes a CRC generation function capable of automatically calculating and appending the 16-
bit CRC frame check sequence (FCS) at the end of each transmitted frame.
The DW1000 also includes a CRC checking function capable of automatically calculating the 16-bit CRC frame
check sequence (FCS) during frame reception and comparing this calculated CRC with the final two octets of
the received frame to check that the calculated CRC matches with CRC transmitted by the frame’s originator.
A mismatch between received and calculated CRC typically indicates that the received frame contains errors
(generally handled by discarding the received frame). At the end of the frame reception as reported via the
RXDFR event status bit, the result of the CRC comparison is reported by either the RXFCG or the RXFCE status
bit being set, i.e. depending on whether or not the CRCs matched. These three status bits are in
0x0F – System Event Status Register
Where a CRC is not required it is possible to suppress the CRC transmission by employing the SFCST
(suppress FCS transmission) bit in
Register file: 0x0D – System Control Register
. This might be done when
using a different MAC layer protocol. This SFCST control is also employed during a throughput maximising
(response-time minimising) technique, as described in section
3.5.2 – TX buffer write while sending
5.2 Frame filtering
Frame filtering is a feature of the DW1000 IC that can parse the received data of a frame that complies with
the MAC encoding defined in the IEEE 802.15.4–2011 standard, identifying the frame type and its
destination address fields, match these against the IC’s own address information, and only accept frames
that pass the filtering rules. See section
11 – APPENDIX 2: The IEEE 802.15.4 MAC
layer for an introduction
to the message format defined in the standard.
The frame filtering functionality allows the IC to be placed into receive mode and only interrupt the host
processor when a frame arrives that passes the frame filtering criteria. When frame filtering is disabled all
frames with good CRC are accepted, typically to interrupt the host with event status indicating a frame has
been received with good CRC (i.e. the RXDFR and RXFCG event status bits are set in
). When frame filtering is enabled the frame filtering rules have to be passed
before these event status (interrupt) bits are set. See section
reception.
Frame filtering is enabled by the FFEN configuration bit in
Register file: 0x04 – System Configuration
. This
register contains seven additional configuration bits (FFAB, FFAD, FFAA, FFAM, FFAR, FFA4 and FFA5) for fine
filtering control of the frame types.
5.2.1 Frame Filtering Rules
If frame filtering is enabled frames will be accepted or rejected based on the following rules:
