DW1000 User Manual
© Decawave Ltd 2017
Version 2.12
Page 71 of 242
Field
Description of fields within Register file: 0x04 – System Configuration
FFA5
reg:04:00
bit:8
Frame Filtering Allow frames with frame type field of 5, (binary 101). IEEE 802.15.4-2011
frames begin with three frame type bits, b3 to b0. The value of binary 100 is not defined in
IEEE 802.15.4-2011. When FFA5 is set to 1, frames of type 5 will be accepted, but no
further frame decoding is done (e.g. no address matching etc.) so software will be
responsible for validating and interpreting these frames. When FFA5 is set to 0, frames of
type 5 will be ignored unless FFAR is set. Section 5.2 describes frame filtering in more
detail.
Note that the frame filter does decode the frame control fields to determine the minimum
length of the expected frame and will reject the frame if it is too short, see section 5.2.
HIRQ_POL
reg:04:00
bit:9
Host interrupt polarity. This bit allows the system integrator the ability to control the
polarity of the IRQ line from the DW1000. When HIRQ_POL is 1 the IRQ output line from
the DW1000 is active high, and, when HIRQ_POL is 0 the IRQ output line from the DW1000
is active low.
Active high operation is recommended for low power applications so that the interrupt is in
its 0 V logical inactive state when the DW1000 is in
or
SPI_EDGE
reg:04:00
bit:10
SPI data launch edge. This bit allows the system integrator the ability to control the launch
edge used for SPI data from the DW1000 on the MISO SPI data output line. This may be
used to select the MISO output operation most suitable to the target system. When
SPI_EDGE is 0 the DW1000 uses the sampling edge to launch MISO data. This setting should
give the highest rate operation. When SPI_EDGE is 1 the DW1000 uses the opposite edges
to launch the data. This setting may give a more robust operation.
DIS_FCE
reg:04:00
bit:11
Disable frame check error handling. This might be of use for protocols using a different
encoding scheme for error handling not based on standard IEEE 802.15.4-2011, but for
normal IEEE 802.15.4-2011 operation this bit should be set to 0. Setting this bit to one
makes the DW1000 treat the frame as valid, ignoring errors, so that in double buffering
mode (for example) it will move on to the next buffer. In normal operation (when DIS_FCE
is 0) with double buffering, a CRC error causes the current RX frame to be discarded and the
buffer to be reused for next frame’s reception.
DIS_DRXB
reg:04:00
bit:12
Disable Double RX Buffer. The DW1000 has a double buffered receiver allowing reception
of a new frame to proceed in one buffer while the host processor is in the process of
unloading the last frame received into the other buffer of the buffer pair. The double
buffering is enabled when DIS_DRXB is set to 0, and disabled when DIS_DRXB is set to 1.
More details on the operation of double buffering are given in section4.3.
DIS_PHE
reg:04:00
bit:13
Disable receiver abort on PHR error. When DIS_PHE is 0 (recommended) the receiver will
discontinue reception when it detects a non-correctable error in the PHY header, see
section
for details of PHR encoding and error correction. The PHR error is
reported by the RXPHE event status bit in
Register file: 0x0F – System Event Status Register
This bit is for debug only and should never be set in an application as it can seriously impair
receiver performance when set.
