Passport 2®/Passport 2 LT™ Service Manual
0070-10-0441
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Theory of Operation
NEC 10.4” Display/Keypad Interface Board
2.14.5
The CPLD Interface to the CPU Board VIA SPI
The purpose of the CPLD (U1) is to interface to and scan for key presses on the front panel
keypad. The method of communicating with the CPLD is the SPI port of the 68HC916X1
communications processor on the CPU control board, 0670-00-0674-XX. The SPI interface is
a serial interface with separate serial data and clock. Data can flow in either direction using
the common clock. The communications processor is set as the master device and the CPLD
can only be a slave.
The serial input provides the keypad poll data (D0, D1, D2, D3) and LED data (XLED1-4) for
the charger and mute LED’s. This data is latched and is updated with each communication
packet and erased whenever the BRESET* is enabled. The output of the keypad Row Select is
sent to the keypad. The column selection is edge latched when a key is pressed. This data is
then serial encoded and transmitted to the Host.
The method used to scan the keypad, which is a matrix of 4 rows (J11, ROW1-4) with up to
8 columns (J10, COL1-8), is a “walking zero” pattern. This means that three out of the four
row lines will always be a logic “1” with one line driven low. In a complete cycle, each line
will sequentially be driven low, driving a different row on the keypad.
The CPLD has an 8-bit receive shift register with a latch to hold the row selection pattern
(walking zero). This completes the first part of the cycle. The next 8 bit serial data received
provides the next pattern for the row selection (walking zero) and simultaneously shifts back
the previous column pattern. If a key were pressed there would be a logic “0” in the data
shifted back for one of the columns. Since the communications processor knows which row
was a logic “0” and now has the column location, it can determine exactly which key was
pressed.
Since there are only four rows allocated to the keypad and eight select lines available, two
have been assigned to the alarm LED’s. The lines used are assigned to bits 4 and 5 of the
input serial data. Lines assigned to bits [0:3] are for the keypad and bits 6 and 7 are not
used. The LED’s can be turned on or off as well as flashed by changing the pattern of the bits
assigned.
Passive components between the CPLD and top and bottom tail connectors are needed as
follows: R15-22 are used to hold the signals high when the signal is low so that there is no
confusion about signal information. Furthermore, R7-14 as well as R23-30 are current
limiting resistors cleaning up the signal to the connectors.
The CPLD is programmed in-circuit by a cable connecting a computer to the 6 pin header, J9.
