Data Translation DT3162, User Manual

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Principles of Operation
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Pixel Clock
The DT3162 provides an internal pixel clock or can accept an external
pixel clock. You select the pixel clock source using software.
The pixel clock locks and synchronizes to the horizontal sync input
signal. Synchronization occurs on the falling edge of the horizontal
sync signal. Once locked and synchronized, the pixel clock generates
the acquisition timing for the board.
The following sections describe the pixel clock sources in more detail.
Internal Pixel Clock
If you select the board’s internal pixel clock, the total pixels per line
(which includes the active and blank pixels) multiplied by the
horizontal frequency determines the frequency of the pixel clock. The
frequency of the internal pixel clock determines the video input
signal digitization rate.
External Pixel Clock
Connector J1 on the DT3162 board accepts two types of external pixel
clock sources:
• Single-ended (TTL) Pixel Clock Input Source
−
This clock
source is accessible on pin C4 of connector J1 on the DT3162. You
can access this signal using the EP332 cable.
Specify ExternalSource1 in software to select this pixel clock
source.
• Differential (LVDS) Pixel Clock Input Source
−
This clock
source is accessible on pin 9 (Pixel Clock
−)
and pin 10 (Pixel
Clock +) of connector J1 on the DT3162. The Camera Interface
Module allows you to attach a TTL-level pixel clock signal
through the CAMERA connector, which is then converted to a
differential LVDS pixel clock input that the DT3162 board uses.