Application Note
(AN241)
PCI-FRM01 Register Level Application Guide
2005 DAQ system, all rights reserved.
http://www.daqsystem.com
7. LVDS(Camera Link) Interface Usage
LVDS(Low Voltage Differential Signal) Interface control
LVDS
LVDS Data register
C0h
Description
I/O Address
Offset
Function
C4h
C8h
CCh
LVDS Command register
LVDS Internal counter register
LVDS Status register
LVDS_DATA
Register
LVDS_CMD
LVDS_CNT
LVDS_STA
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Data
LVDS
Data Register Bit Position & meaning
D31
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
D0
0
1
2
3
4
31
Reserved
LVDS
Command Register Bit Position & meaning
5
D
I
E
R
S
Bit
Name
Description
Default
Value
0
Enable
Used for simulation
‘
0
’
1
Reset
‘
0
’
2
Data
Enable
‘
0
’
3
Interrupt
Enable
‘
0
’
4
Start
‘
0
’
15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Line Counter
LVDS
Internal counter Register Bit Position & meaning
L15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Pixel Counter
P0
P15
L0
