Application Note
(AN241)
PCI-FRM01 Register Level Application Guide
2005 DAQ system, all rights reserved.
http://www.daqsystem.com
3. I/O Address Usage
The below table indicates the base address of the peripheral device that is located I/O area address.
The table below the I / O area is located at the address indicates the base address of the peripheral
device. All I / O registers are 32-bit input / output processing.
Reserved area for future use
00h-5Fh
Description
I/O Address
Offset Base
Reserved
Function
60h
70h-AFh
Universal asynchronous receiver transmitter (RS232C)
Reserved area for future use
UART
Reserved
Frame grabber LVDS interface
C0h
D0h
E0h-FFh
Photo-coupler isolated Digital input/Output
Reserved area for future use
Camera Link
DIO
Reserved
Comment
B0h
Interrupt controller
Interrupt
