PCI-EK01 Users Manual (Rev 1.0)
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http://www.daqsystem.com
Very fle xible to upgrade b ecause of FPGA is used as PCI bridge and
overall board
Analog Input
12bit resolution/ 8 Single ended or 4 differential input
0 to +3.3V, ± 1.65V input r ange/ MAX 200 Ksps(5uSEC) conve rsion
time
Can change sampling interv al in auto scanning mode by 2.5uSEC
increment
Po wer on auto -calibration / ± 1 (LSB) INL/ DNL
± 1uA analog input leakage current/ 20pF analog input capacitance
On-board 1024 x 16 data FIFO/ On -board 256K(t yp e A) x 16 data
SRAM
Analog Output
12bit resolutio n/ 4 channel output/ 0 to +3.3V outpu t range
MAX 1 M (1u SEC) update rate
Can change update interval in wa veform generation mode by 1uSEC
increment
Simultaneous update of outputs
± 16 (LSB) INL/ ± 1 (LSB) DNL/ ± 3 (LSB) Offset er ror/ Sle w Rate
0.7V/usec
On-board 1024 x 16 wa ve form generation dual -port RAM
Digital I/O
On-board 82C55 chip/ 2 4bit general purpose I/O
Three 8bit group (Port A/B/C)/ 3.3V CMOS logic le vel
Port B has high current si nk capability (ma x 500mA)
Timer/Counter
32-bit Timer/ 32 -bit Count er
Input frequency ma x 60 Mhz/ 25n timer resolution
One-shot or alternate tim er output mode/ 3.3V CMOS logic level
Software
Supported OS
W indows 2000/XP /W indows 7
API
Kernel mode W DM Dri ver/ User mode DLL
Test Application(W aveform Generator, W aveform Display)
