Chapter 4
Signal Connections
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National Instruments Corporation
4-39
PCI-MIO E Series User Manual
As an output, the UPDATE* signal reflects the actual update pulse that
is connected to the DACs. This is true even if the updates are being
externally generated by another PFI. The output is an active low pulse
with a pulse width of 300 to 350 ns. This output is set to tri-state at
startup.
show the input and output timing requirements
for the UPDATE* signal.
Figure 4-26. UPDATE* Input Signal Timing
Figure 4-27. UPDATE* Output Signal Timing
The DACs are updated within 100 ns of the leading edge. Separate the
UPDATE* pulses with enough time that new data can be written to the
DAC latches.
The PCI-MIO E Series board UI counter normally generates the
UPDATE* signal unless you select some external source. The UI
counter is started by the WFTRIG signal and can be stopped by software
or the internal Buffer Counter.
Rising-edge
polarity
Falling-edge
polarity
tw
tw = 10 ns minimum
t w
t w = 300-350 ns
