USB3-FRM20 User’s Manual
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2-2. Board Description
As shown in the figure below, in the case of USB3-FRM20, the overall control is in charge of
FPGA Core Logic. Its main function is to transmit C-PHY or D-PHY MIPI Image Frame Data signals
through the External I/O connector. These functions are performed using API in PC through USB
3.0 interface.
External I/O connector uses 2x20 2.54mm Pitch Male Header connector to connect to MIPI
sensor board connector, and 2x16 2.54mm Pitch Male Header connector (J4, J5) to connect with
our MIPI-PWR02 power board. For detailed connector signal specifications, refer to Section 2.3
and Appendix A1.
[Figure 2-2. USB3-FRM20 Block Diagram]
The program of the FPGA core logic uses JTAG, and functions to save the logic program in
the FPGA Program Logic and download it when power is applied.
Note) In case of USB connection, USB2.0 interface, which is insufficient for high-speed
image transfer, is not supported. Only the USB3.0 interface is used.
