PCIe-FRM13 User’s Manual
7
2-2 FPGA Block Diagram
The FPGA core logic is programmed using JTAG, and the logic program is saved in FPGA
Program Logic and loaded when power is applied.
PCI Target
/ Master
PCI Express
1x BUS
Local Bus
Address
Data(Mem,I/O)
Reserved
(0x00
–
0x5F)
Reserved
(0x70
–
0xAF)
UART
(0x60)
Camera Link(LVDS)
(0xC0)
Interrupt controller
DIO
(0xD0)
Ext. Address, Data, Control
Local BUS
Interrupt
Controller
(0xb0)
INT sources in Chip
IO Decoder
MEM Decoder
To each IO
Module
PCIe-FRM13 INTERNAL BLOCK - FPGA
DPRAM
From Ext.
CLOCK syn.
MEM Decoder
BUS Mux
Reserved
(0xE0
–
0xFF)
[Figure 2-2. PCIe-FRM11 FPGA Block Diagram]
