PCIe-FRM13 User’s Manual
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2-5 Camera Link & PCIe-FRM13
PCIe-FRM13 supports Camera Link Base Configuration. Base Configuration consists of 4 LVDS
signal lines serializing 28-bit parallel signals including 24 data bits and 4 enable signals Frame
Valid, Line Valid, Data Valid, and a spare, and 1 LVDS signal line to synchronize with the camera. ,
Asynchronous serial communication including 4 CC (Camera Control) signals and 2 LVDS lines for
asynchronous serial communication to communicate with the camera are transmitted through
MDR cables.
The transmitted signal deserilizes 4 video LVDS serial signals into 28-bit parallel video signals
and control signals (Frame Valid, Line Valid, Data Valid, and a spare) through the Channel Link chip
in PCIe-FRM13. In addition, a clock signal is made with one LVDS to synchronize the signal
between the camera and PCIe-FRM13, and the remaining cameras control signals and
communication signals are converted into general TTL signal levels and used.
CCx+
CCx-
Camera Control
The figure shows the Camera Control output circuit that can send the control signal from the
PCIe-FRM13 board to the Camera through the Camera-link cable. A total of 4 digital outputs are
output through the differential method. Each output is mapped to a digital output and becomes
an output. Each bit position is shown in [Figure 2-7] below.
CC1+
CC1-
CC_D0
CC2+
CC2-
CC_D1
CC3+
CC3-
CC_D2
CC4+
CC4-
CC_D3
[Figure 2-7. Camera Control LVDS Digital Output Circuit]
