42
PRELIMINARY
1M28, 1M75, and 1M150 User’s Manual
03-32-00525-04
DALSA
Bit 0 of status register 4 indicates a transmission error during RS232 communication. This flag can
be used to catch errors during read operations. Bit 1 of status register 4 indicates access to an
undefined register. With read operations producing the result 18H=Cancel, this bit can be used to
distinguish between correct responses of the camera and an undefined state.
Table 14: Status Register 4 (Register address REGADDR = 5D = 05H)
Register address 5 – STATUS4_REG
Bit
Description
0
Error in the asynchronous communications transfer
1
CANCEL was active, i.e. read from non defined register
2
Not used = 0
3
Not used = 0
4
Not used = 0
5
Not used = 0
6
Not used = 0
7
Not used = 0
Register Address 06H and 07H (Mode Register 0 and 1)
Mode registers 0 and 1 control the basic functions of the camera. To ensure proper operation, these
registers are updated first during power-up. The functions of each individual bit are shown in the
following tables.
Table 15: Mode register 0 (Register address REGADDR = 6D = 06H)
Register address 6 - MODE0_REG
Bit
Name
Description
Default
0
ENABLE0
Camera on, = 1
Î
Camera in operation
1
1
ENABLE1
Invert Pixel Clock, = 1
Î
phase shift of 180 degrees
0
2
ENABLE2
0
3
ENABLE3
These bits are responsible for resolution, access to the
LUT’s and the LFSR interface test
0
4
EN_TOGGLE
= 1
Î
Automatic voltage switching active
1
5
EN_LL2_LOG
= 1
Î
LinLog2-response curve active
0
6
LOG
= 1
Î
Log response curve on
= 0
Î
Log response curve off
0
7
LINLOG
= 1
Î
LinLog-response curve on
= 0
Î
LinLog-response curve off
0
If the camera is deactivated by bit 0 register 6, then the internal ADC, as well as, internal and
external triggers are also deactivated.
To test the camera interface and connection to the framegrabber, bits 2 and 3 control the pseudo-
random number generator with an 8 bit Linear Feedback Shift Register (LFSR). The pseudo-
random number generator resets itself at the beginning of each line allowing you to determine the
reliability of the interface. For more information on the LFSR, refer to Appendix D.
Bit 4 activates the automatic switching of the camera’s LinLog and Skim factory settings to
predefined LinLog and Skim settings. It also controls automatic offset compensation when
switching to a high gain (bit7 register 7) and the activation of the classical logarithmic mode (bit 6