9
EXPECTED RECORD TIME (80GB HDD use)
8
NVP3000 PIN ASSIGNMENT
0.005
0.007
0.013
Mbps
77672.3 Hour
51781.5 Hour
27740.1 Hour
0.03fps
14
0.0023
0.0035
0.0066
Mbps
0.016
0.023
0.044
Mbps
23301.7 Hour
15534.5 Hour
8322.0Hour
0.1fps
12
0.008
0.012
0.022
Mbps
38836.1 Hour
25890.8 Hour
13870.1 Hour
0.06fps
13
1165.1Hour
776.7Hour
416.1Hour
2fps
7
0.16
0.23
0.44
Mbps
2330.2Hour
1553.4Hour
832.2Hour
1fps
8
0.078
0.117
0.219
Mbps
4660.3Hour
3106.9Hour
1664.4Hour
0.5fps
9
0.039
0.059
0.109
Mbps
7767.2Hour
5178.2Hour
2774.0Hour
0.3fps
10
0.016
0.023
0.066
Mbps
155.3Hour
103.6Hour
55.5Hour
15fps
3
1.2
1.8
3.3
Mbps
233.0Hour
155.3Hour
83.2Hour
10fps
4
0.8
1.2
2.2
Mbps
466.0Hour
310.7Hour
166.4Hour
5fps
5
0.39
0.59
1.09
Mbps
776.7Hour
517.8Hour
277.4Hour
3fps
6
0.23
0.35
0.66
Mbps
11650.8 Hour
7767.2Hour
4161.0Hour
0.2fps
11
38.8Hour
25.9Hour
13.9Hour
60fps
1
4.7
7.0
13.1
Mbps
77.7Hour
51.8Hour
27.7Hour
30fps
2
LOW
MIDDLE
HIGH
UNIT
2.3
3.5
6.6
Mbps
LOW
MIDDLE
HIGH
PIC.Quality
REC LEVEL
10
15
28
KB
File size/1f
–Storage (29-pin)
•DATA [15:0 ] :Storage data inout
•CSN1 :Storage address output
•CSN0 :Storage address output
•ADDR [2:0 ] ::Storage address output
•IOWN :Storage write strobe output
•IORN :Storage read strobe output
•INTRQ :Storage interrupt input
•RSTN :Storage reset output
•IORDY :Storage ready signal input
•DEN :Data bus control input
•ACC_REQ :External bus access request
•WR_RD :External bus write/read access strobe
–TEST0/TES1/BND/TEST (4-pin)
•TEST0,TEST1 :Chip operation mode selection input
•FLASH :Chip bonding option selection input
•TEST :Chip test input pin for storage device reset point
–SDRAM_E (36-pin)
•CLK54O_E :SDRAM driving clock output
•RASB :Row address strobe output
•CASB :Column address strobe output
•WEB :Write enable output
•DQM0 :Data(DQ)mask output
•DQM1 :Data(DQ)mask output
•DATA [15:0 ] ::Data bus inout
•ADDR [11:0 ] ::Address bus output
•BA [1:0 ] :Bank selection output
–CLK54I/RSTB/TRIG_OUT/TCLK/TDATA (5-pin)
•CLK54I :54MHz main clock input
•RSTB :Global reset input
•TRIG_OUT :External trigger signal output
•TCLK :Serial channel ID decoding strobe
•TDATA :Serial channel ID decoding data
Summary of Contents for DX-N111N
Page 12: ...20 SCHEMATICS 1 CONNECTION DIAGRAM 3 0 COMBO...
Page 13: ...21 SCHEMATICS 2 BLOCK DIAGRAM...
Page 14: ...22 SCHEMATICS 3 FRONT SCHEMATIC DIAGRAM S A 3 0 COMBO...
Page 15: ...23 CIRCUIT DIAGRAM 4 JACK SCHEMATIC DIAGRAM...
Page 16: ...24 CIRCUIT DIAGRAM 5 POWER SCHEMATIC DIAGRAM...
Page 17: ...25 6 SYSCON SCHEMATIC DIAGRAM CIRCUIT DIAGRAM...
Page 18: ...26 CIRCUIT DIAGRAM 7 VIDEO AUDIO SCHEMATIC DIAGRAM...
Page 19: ...27 CIRCUIT DIAGRAM 8 CODEC SCHEMATIC DIAGRAM...
Page 20: ...28 COMPONENTS LOCATION GUIDE ON PCB BOTTOM VIEW 1 1 VCR MAIN...
Page 21: ...29 COMPONENTS LOCATION GUIDE ON PCB BOTTOM VIEW 1 2 POWER...