7
NVP3000 PIN ASSIGNMENT
6
NVP3000 PIN ASSIGNMENT
total user IO pin : 167-pin
VIN
AIN
AOUT
VOUT
SDRAM_E
TRIG/TCLK/TDATA/
CLK54I/RSTB
TEST0/TEST1/
BND/TEST
STORAGE
MICOM
KEY
JOG-
SHUTTLE
SDRAM_D
9
2
3
9
5
36
36
4
29
16
6
12
–VIN (9-pin)
•CLK27I :27MHz clock input
•VIN [7:0 ] ::Video data input
–AIN (2-pin)
•AIN :Serial audio data input
•RSYNC :Audio data receive sync output
–AOUT (3-pin)
•AOUT :Serial audio data output
•BCLK :Serial bit clock output
–VOUT (9-pin)
•CLK27O :27MHz clock output
•VOUT [7:0 ] ::Video data output
–SDRAM_D (36-pin)
•CLK540_D :SDRAM driving clock output
•RASB :Row address strobe output
•CASB :Column address strobe output
•WEB :Write enable output
•DQM0 :Data(DQ)mask output
•DQM1 :Data(DQ)mask output
•DATA [15:0 ] ::Data bus inout
•ADDR [11:0 ] ::Address bus output
•BA [1:0 ] :Bank selection output
–KEY (12-pin)
•KEY_DATA [5:0 ] ::Key scan row address output
•KEY_SEL [5:0 ] ::Key data input
–JOG-SHUTTLE (6-pin)
•JOG [1:0 ] :Jog signal input
•SHUTTLE [3:0 ] ::Shuttle signal input
–MICOM (16-pin)
•MADDR [2:0 ] ::Indirect register address input
•CSN :Chip select input
•WEN :Write enable input
•RDN :Read enable input
•INTRQ :Interrupt output
•MDATA [7:0 ] ::Data inout
•NWRDY :network ready strobe
Summary of Contents for DX-N111N
Page 12: ...20 SCHEMATICS 1 CONNECTION DIAGRAM 3 0 COMBO...
Page 13: ...21 SCHEMATICS 2 BLOCK DIAGRAM...
Page 14: ...22 SCHEMATICS 3 FRONT SCHEMATIC DIAGRAM S A 3 0 COMBO...
Page 15: ...23 CIRCUIT DIAGRAM 4 JACK SCHEMATIC DIAGRAM...
Page 16: ...24 CIRCUIT DIAGRAM 5 POWER SCHEMATIC DIAGRAM...
Page 17: ...25 6 SYSCON SCHEMATIC DIAGRAM CIRCUIT DIAGRAM...
Page 18: ...26 CIRCUIT DIAGRAM 7 VIDEO AUDIO SCHEMATIC DIAGRAM...
Page 19: ...27 CIRCUIT DIAGRAM 8 CODEC SCHEMATIC DIAGRAM...
Page 20: ...28 COMPONENTS LOCATION GUIDE ON PCB BOTTOM VIEW 1 1 VCR MAIN...
Page 21: ...29 COMPONENTS LOCATION GUIDE ON PCB BOTTOM VIEW 1 2 POWER...