(2) Block Diagram
13
6
I²C
in
terf
ace
(5
6)
19
a
d
r/
td
i
scl
sd
a
V DA
C
(5
4)
U DA
C
(5
3)
Y DA
C
(5
2)
OF
FS
E
T
GA
IN
76
2
79
GA
IN
OF
FS
E
T
OF
FS
E
T
GA
IN
A
DC1
(2)
52
63
62
61
53
54
58
55
56
57
39
40
41
48
37
46
47
GA
IN
A
DC2
(3)
GA
IN
So
ur
c
e
Se
lect
(1)
So
ur
c
e
Se
lect
(16
)
38
AD
CR
(12
)
GA
IN
A
DCG
(13
)
GA
IN
AD
CB
(14
)
GA
IN
AD
CF
(15
)
GA
IN
Not
c
h
De
skew
(4)
Sy
nc
(6)
Co
lo
r
De
co
der
(5)
de
lay
co
ntr
o
l
(P
AL/
S
E
C
AM
)
(7)
1H
de
lay
18
20
An
ti
alias
,
D
esk
ew
(1
7)
An
ti
alias
,
D
esk
ew
(1
8)
An
ti
alias
,
D
esk
ew
(1
9)
An
ti
alias
,
D
esk
ew
(2
0)
te
st
-
co
n
tro
ller,
me
mo
ry
b
ist
(5
5)
71
7
tc
lk
tm
s
69
70
xt
al
osc
illat
o
r
(9)
xo
u
t
xi
n
di
v
ide
r
32
31
30
15
22
21
16
10
9
74
8
IT
U65
6
De
c
o
d
e
r
(41
)
656
h
in
/
cl
kf
2
0
656v
in/
blank
CLK
F
2
0
RG
B
!
YU
V
or
by
pa
s
s
(25
)
τ
(27
)
Y
br
ig
ht
ne
s
s
con
trast
(2
6)
U,V
satu
rat
ion
O
ff
set
,
Gai
n
(29)
(
3
0)
s
o
ft
-mi
x
ch
an
ne
l
mux
(31
)
do
w
n
sa
mp
lin
g
2
4:
4:
4
!
4:
2:
2
(2
8)
H-
pres
caler
(34
)
no
ise
m
easu
re
me
nt
(3
2)
cl
am
pin
g
c
o
rrec
tio
n
(21)
cl
am
pin
g
c
o
rrec
tio
n
(22)
cl
am
pin
g
c
o
rrec
tio
n
(23)
DC
TI
(46)
Pe
akin
g
(45)
Co
ars
e
Del
a
y
4:
4:
4
(4
9)
IT
U6
56
E
n
c
ode
r
(5
1)
8
8:
8:
8
(50)
Fi
ne
de
la
y
Y n
o
ise
re
duc
ti
o
n
(3
8)
UV
no
is
e
re
duc
ti
o
n
(3
7)
e
DRA
M
me
mo
ry
c
ont
ro
ll
e
r
(3
9)
14
23
17
27
P
ixelm
ixer
(44)
H-
po
stscaler
(4
2)
Pa
n
o
ra
m
a
ge
n
e
ra
tor
(4
3)
V
H
av
out
auou
t
ay
out
hout
vo
u
t
cl
k
o
u
t
v5
0
h5
0
v
cv
bs
o
3
cvb
so
2
cvb
so
1
cvb
s1
cvb
s2
cvb
s3
cvb
s4
cvb
s5
cvb
s6
cvb
s7
ri
n
1
gin1
bin1
ri
n
2
gin2
bin2
fbl2
fbl1
656c
lk
6
56io0
6
56io1
6
56io2
6
56io3
6
56io4
6
56io5
6
56io6
6
56io7
CL
A
M
P
CL
A
M
P
c
lam
p
ing
s
ign
al
s
to
A
DCs
AGC
g
ene
ra
to
r
Y d
e
lay
(8
)
PRIMUS
(B
13/
B
14)
VSP94x2A
CLK
B
3
6
Y
U,
V
C
V
BS/
Y
C
YC
SE
L
Y
U,
V
Y
U
V
F
α
main
in
s
e
rt
CLK
F
2
P
AD
UV
in
Y
in
da
ta
buff
er
data
bu
ffer
24
re
se
t
lin
e l
o
c
ked
or
fr
e
e
-r
u
nni
ng
di
v
ide
r
line
-l
o
cke
d
cl
o
cks
(36
, 72
M
H
z
)
fr
ee-
ru
nning
cl
o
cks
(2
0.
25
, 40
.5
M
H
z
)
c
la
m
pe
d,
fi
lt
erd
s
y
nc
s
igna
l
Out
put
Da
ta
C
o
nt
ro
ller
(5
5)
rea
d
co
nt
ro
l
H/
V
-
a
c
qu
isi
tion
(3
3)
In
put
Sy
n
c
Ou
tp
ut
Syn
c
Ba
ck
gr
o
u
n
d
ge
ne
ra
to
r
(57)
Out
put
Syn
c
C
o
nt
ro
ller
(4
0)
64
8
M
H
z
DT
O
(1
0)
LL-
P
L
L
(11
)
64
8
MHz cl
k
21
6 M
H
z
c
lk
line
-l
oc
k
e
d
BL
AN
K
BL
AN
EN
BL
A
N
K
FB
940x
A,
943
x
A
on
ly
80
78
79
77
75
76
i6
5
6
ic
lk
1
2
3
i65
6
i0
i65
6
i1
i65
6
i2
i65
6
i3
i65
6
i4
i65
6
i5
i65
6
i6
i65
6
i7
to
65
6dec
od
er
9
41xA
,
94
4
x
A
on
ly
le
tt
e
rbo
x
de
te
c
ti
o
n
(58
)
6
IC DESCRIPTION
APPENDIX
Summary of Contents for DTM-29U7Z SERIES
Page 5: ...4 CIRCUIT BLOCK DIAGRAM...
Page 13: ...12 SCHEMATIC DIAGRAM...
Page 14: ...13...
Page 15: ...14 EXPLODED VIEW DTM 29U7ZLS DTM 29U7ZZS...
Page 17: ...16 DTM 28W8ZLS DTM 28W8ZZS EXPLODED VIEW...
Page 18: ...17 EXPLODED VIEW DTM 2881ZLS 2881ZZS...
Page 19: ...PRINTED CIRCUIT BOARD 18...
Page 20: ...PRINTED CIRCUIT BOARD 19...
Page 21: ...PRINTED CIRCUIT BOARD 20...
Page 35: ...3 3 Block Diagram IC DESCRIPTION APPENDIX...
Page 50: ......