Daewoo DTM-29U7Z SERIES, Service Manual

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1
IC DESCRIPTION
5-1. ST92195
(1) General Description
1.1 INTRODUCTION
The ST92195 microcnontoller is developed and manufac-
tured by STMicroelecrtonics using a proprietary n-well
HCMOS process. Its performance derives from the use of
a flexible 256-register programming model for ultra-fast
context switching and real-time event response. The intel-
ligent onchip peripherals offload the ST9 core from I/O
and data management processing tasks allowing critical
application tasks to get the maximum use off core
resources. The ST92195 MCU supports low power con-
sumption and low voltage operation for power-efficient
and low-cost embedded systems.
1.1.1 ST9+Core
The advanced Core consists of the Central Processing
Unit (CPU), the Register File and the Interrupt controller.
The general-purpose registers can be used as accumula-
tor, Index register, or address pointers. Adjacent register
pairs make up 16-bit registers for addressing or 16-bit
processing. Although the ST9 has an 8-bit ALU, the chip
handles 16-bit operations, including arithmetic, loads/
stores, and memory/register and memory/memory
exchanges. Two basic memory spaces are available :
Program Memory and the Register File, Which includes
the control and status registers of the on-chip peripherals.
1.1.2 Power Saving Modes
To optimize performance versus power consumption, a
range of operating modes can be dynamically selected.
Run Mode.
This is the full speed execution mode with
CPU and peripherals running at the maximum clock
speed delivered by the phase Locked Loop(PLL) of the
Clock Control Unit(CCU).
Wait For Interrupt Mode.
The Wait For Inter-
rupt(WFI) instruction suspends program execution until
an interrupt request is acknowledged. During WFI, the
CPU clock is halted while the peripheral and interrupt
controller keep running at a frequency programmable via
the CCU. In this mode, the power consumption of the
device can be reduced by more than 95%(LP WFI).
Wait For Interrupt Mode.
The Wait For Inter-
rupt(WFI) instruction, and if the Watchdog is not enable,
the CPU and its peripherals stop operation and the I/O
ports enter high impedance mode. A reset is necessary to
exit from Halt mode.
1.1.3 I/O Ports
Up to 28 I/O lines are dedicated to digital Input/Output.
These lines are grouped into up to five I/O Ports and can
be configureed on a bit basis under software control to pro-
vide timing, status signals, timer and output, analog inputs,
external interrupts and serial or parallel I/O.
1.1.4 TV Peripherals
A set of on-chip peripherals form a complete system for TV
set and VCR applications:
- Voltage Synthesis
- VPS/WSS Slicer
- Teletext Slicer
- Teletext Display RAM
- OSD
1.1.5 On Screen Display
The human interface is provided by the On Screen Display
module, this can produce up to 26 lines of up to 80 charac-
ters from a ROM defined 512 character set. The character
resolution is 10x10 dot. Four character sizes are sup-
ported. Serial attributes allow the user to select foreground
and background. Parallel attributes can be used to select
additional foreground and background colors and underline
on a character by character basis.
1.1.6 Teletext and Display RAM
The internal 8k Teletext and Display storage RAM can be
used to store Teletext pages as well as Display parame-
ters.
1.1.7 Teletext, VPS and WSS Data Slicers
The three on-board data slicers using a single external
crystal are used to extract the Teletext, VPS and WSS
information from the video signal. Hardware Hamming
decoding is provided.
1.1.8 Voltage Synthesis Tuning Control
14-bit Voltage Synthesis using the PWM (Pulse Width
Modulation)/BRM (Bit Rate Modulation) technique can be
used to genetate tuning voltages for TV set applications.
The tuning voltage is output on one of two separate output
pins.
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