18
CIRCUIT OPERATING MANUAL
* The functions of individual Pin.
PIN NAME
PIN No.PIN DESCRIPTION
LNB POWER B
1
LNB Voltage supply. To put 1000PF of ceramic capacitor into ground.
LNB POWER A
2
LNB Voltage supply. To put 1000PF of ceramic capacitor into ground.
A-GND
3,6
GND. Please don t let any Digital Noise enter through ground.
B1
4
5V Supply for RF Amp TR
B2
5
5V Supply for ZERO-IF chip(for RF)
B3
6
5V Supply for ZERO-IF chip(for PLL)
A/S
8
I
2
C Bus Address selection input (See table 3)
T/M
9
Tuning voltage monitor (Do not connect it to anywhere)
30V)
10
PLL channel select voltage supply (+30V)
B4
11
5V supply for AGC pull-up
NRES
12
Reset, active at low level.
AUX_CLK
13
Programmable Output Port or Programmable Output Clock
F22/DiSEqC
14
DiSEqC modulation (22kHz Tone), Programmable Output Port
SCL
15
I
2
C Bus
SDA
17
N.C
16
Do not connect it to anywhere
BCLK OUT
18
Output Byte Clock; or Bit Clock in Serial Mode.
N.C
19
Do not connect it to anywhere
DO,....,D7
20~27
Output Data : D7 is DATA_OUT in Serial Mode.
N.C
28
Do not connect it to anywhere
D/P
29
Data/Parity Signal.
ERROR
30
Output Error Signal. Set in case of uncorrectable packet.
STR OUT
31
Output 1st byte Signal (synchro byte clock)
VDD
32
+3.3V Supply for LINK IC
Chart 5. Tuner Module Pin Out
Data
Parity
No Error
Uncorrectible Packet
No Error
BYTE CLK
P A C K E T
STR OUT
E R R O R
BY T E D A T A
Feature 11. Parallel Data Output Timing
TS Output is made by the Serial or Parallel function.
The relationship between TS output Data and Control signal is showing in the following diagram. If an error occurs Data is
ignored, and the Data in the Valid area is valid.
Parallel Output Timing
Summary of Contents for DSD-9251MA
Page 17: ...16 CIRCUIT OPERATING MANUAL Feature 9 EMI Interface Timing...
Page 40: ...39 39 SCHEMATIC DIAGRAM...
Page 41: ...40 40 SCHEMATIC DIAGRAM...
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Page 49: ...48 48 SCHEMATIC DIAGRAM...
Page 50: ...49 49 SCHEMATIC DIAGRAM...
Page 51: ...50 ELECTRICAL PARTS LIST 50...
Page 52: ...51 51 EXPLODED VIEW...
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