
Module Documentation
FM4, S6E2DH/S6E2DF/S6E2D5/S6E2D3 Series, 32-Bit Microcontroller, Graphic Driver User Manual, Doc. No. 002-04387 Rev. *A
131
11.6.5.15 MML_GDC_PE_API MM_ERROR mmlGdcPeRopOperation ( MML_GDC_PE_CONTEXT
pectx, MM_U08 op_red, MM_U08 op_green, MM_U08 op_blue, MM_U08 op_alpha )
Set the Raster Operation (ROP) for each color channel and the alpha channel. If pectx is equal to NULL,
mmlGdcPeRopOperation is terminated without any operation.
Note:
The involved source surfaces depend of the ROP mode. The driver will report an error if a requested surface
is not defined and mmlGdcPeBlt is called.
If one of the ROP modes uses the DST surface, the blend unit in the blit path will be switched off and the
result will be written directly in the store surface.
If there is a MASK surface, by default MASK buffer alpha channel is read as extern alpha value of SRC
surface. If one of the ROP modes uses the MASK surface the extern alpha path of the SRC surface will be
switched off and the MASK surface is the input of ROP operation.
The required ROP mode can be calculated by the following table:
surface DST MASK SRC output (STORE)
0
0
0
0
0
0
1
1
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
1
0
1
1
1
1
1
Operation index
0x5B
Some useful ROP modes are predefined in the define section of this file, see MML_GDC_PE_ROP_...
Parameters
in,out
pectx
Pixel Engine context (!=NULL).
in
op_red
ROP3 operation code for red component (default: MML_GDC_PE_ROP_SRCCOPY).
in
op_green
ROP3 operation code for green component (default: MML_GDC_PE_ROP_SRCCOPY).
in
op_blue
ROP3 operation code for blue component (default: MML_GDC_PE_ROP_SRCCOPY).
in
op_alpha
ROP3 operation code for alpha component (default: MML_GDC_PE_ROP_SRCCOPY).
Return values
MML_OK
On success. Otherwise the related error code.