CHAPTER1: Flash Memory
4. Registers
P E R I P H E R A L M A N U A L
38
S6E1Cx_MN710-00016-1v0-E, August 31, 2015
CONFIDENTIAL
4.7
Flash Sync Down Register (FSYNDN)
The wait cycle is inserted in the read access to the flash memory. Current consumption can be reduced by
decreasing the access clock frequency of the flash memory.
Register Configuration
bit
7
6
5
4
3
2
1
0
Field
Reserved
SD
Attribute
-
R/W
Initial Value
-
0001
Register Functions
[bit7:4] Reserved bits
The read values are undefined. Ignored on write.
[bit3:0] SD : Sync Down
Specifies the wait cycle inserted in the read access of the flash memory.
Bit
Description
0000
Setting prohibited
0001
1 wait cycle (Initial value)
0010
Setting prohibited
0011
3 wait cycles
0100
Setting prohibited
0101
5 wait cycles
0110
Setting prohibited
0111
7 wait cycles
1000
Setting prohibited
1001
9 wait cycles
1010
Setting prohibited
1011
11 wait cycles
1100
Setting prohibited
1101
13 wait cycles
1110
Setting prohibited
1111
15 wait cycles
Notes:
−
The register is valid only when RWT bits in FRWTR register is set to "111". Otherwise the value of
this register is ignored.
