PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
143
17. POR and LVD
This chapter briefly discusses the Power on Reset (POR) and Low Voltage Detect (LVD) circuits and their associated regis-
ters. For a complete table of the POR registers, refer to the
Summary Table of the System Resource Registers on page 106
For a quick reference of all PSoC registers in address order, refer to the
Register Reference chapter on page 187
.
17.1
Architectural Description
The Power on Reset (POR) and Low Voltage Detect (LVD) circuits provide protection against low voltage conditions. The
POR function senses Vcc and Vcore (regulated voltage) holding the system in reset until the magnitude of Vcc and Vcore
supports operation to specification. The LVD function senses Vcc and provides an interrupt to the system when Vcc falls
below a selected threshold. Other outputs and status bits are provided to indicate important voltage trip levels. Refer to
tion 16.2 Pin Behavior During Reset
for a description of GPIO pin behavior during power up.
Summary of Contents for PSoC CY8CTMG20 Series
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