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Introduction 

CY4502 EZ-

PD™ CCG2 Development Kit Guide, Doc. No. 001-96601 Rev. *B 

1.4   Abbreviations 

Table 1-2. List of Abbreviations 

Definitions and 

Acrynoms  

Meaning 

Active cable 

 

Electronically Marked Cable Assembly with a re-driver to condition USB data signals.

 

Biphase 

Mark 

Code 

(BMC) 

 

Modification of Manchester code in which a zero has one transition and a one has two transitions. 

 

Cable plug 

 

Term used to describe a PD-

capable element in a multidrop system addressed by SOP’/SOP’’ packets. 

Logically,  the  cable  plug  is  associated  with  a  USB  plug  at  one  end  of  the  cable.  In  a  practical 
implementation, the electronics may reside anywhere in the cable. 

 

Configuration 

channel 

(CC) 

 

Single wire used by the BMC PHY layer signaling in Type-C. 

 

CRC 

Cyclic Redundancy Check - The USB PD packet header and data shall be protected by a 32-bit CRC 

DFP

 

Downstream facing port is a USB Type-C port on a host or a hub to which devices are connected.

 

DVK

 

Development kit.

 

EEPROM

 

Electrically erasable programmable read-only memory.

 

Electronically Marked 
Cable Assembly  

(EMCA) 

A USB Type-

C cable that uses USB PD to provide the cable’s characteristics 

 

End Of Packet (EOP) 

K-code marker used to delineate the end of a packet 

 

I

2

C

 

Inter-integrated circuit. 

Packet 

 

An entire unit of PD communication, including a preamble, SOP, payload, CRC, and EOP. 

 

Passive cable 

 

Cable with a USB plug on each end, at least one of which is a cable plug supporting SOP’ that does not 
incorporate  data  bus  signal  conditioning  circuits.  Supports  the  Structured  VDM  to  determine  its 
characteristics

Type-C specification

 does not discuss passive cables that are not EMCAs. 

 

PC 

Personal computer. 

SBU 

Sideband  Use  Signals  are  used  in  the  Alternate  Mode  supported  by  the  Type-C  specification,  which 
enables multi-purposing of Type-C signals for alternate uses such as DisplayPort 

SCL 

I

2

C serial clock line. 

SDA 

I

2

C serial data line. 

SDK 

Software development kit. 

Start of packet (SOP)  

K-code marker used to delineate the start of a packet. Three SOP sequences are 

defined: SOP, SOP’, 

and SOP’’, with SOP* used to refer to all three.  

SOP packet  

PD packet that starts with an SOP.  

SOP’ packet  

PD packet that starts with an SOP’; used to communicate with a cable plug at the near end/host side of 
the cable.  

SOP’’ packet  

PD packet that starts with an SOP’’; used to communicate with a cable plug at the far end/device side of 
the cable.  

Summary of Contents for EZ-PD CY4502

Page 1: ...CY4502 EZ PD CCG2 Development Kit Guide Doc No 001 96601 Rev B Cypress Semiconductor 198 Champion Court San Jose CA 95134 1709 Phone USA 1 800 858 1810 Phone Intnl 1 408 943 2600 http www cypress com...

Page 2: ...d States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create deri...

Page 3: ...12 2 3 Install Software 12 2 4 Uninstall Software 12 3 Kit Operation 13 3 1 Theory of Operation 13 3 2 Jumpers 14 3 3 CCG2 Single Chip EMCA Application 15 3 4 CCG2 Two Chip EMCA Application One Chip...

Page 4: ...No 001 96601 Rev B 4 Appendix A Troubleshooting Guide 34 Appendix B PCB Layout 35 B 1 Top Layer 35 B 2 Bottom Layer 35 B 3 Ground Layer 1 36 B 4 Ground Layer 2 36 B 5 Power Layer 1 37 B 6 Power Layer...

Page 5: ...on ESD can damage boards and associated components Cypress recommends that the user perform procedures only at an ESD workstation If an ESD workstation is not available use appropriate ESD protection...

Page 6: ...board provided with the DVK It documents different types of firmware downloading and debugging methods with detailed instructions This guide briefly explains the hardware interfaces available on the d...

Page 7: ...b page for additional learning resources including a datasheet a technical reference manual application notes knowledge base articles and training videos Visit the CCG1 web page for additional informa...

Page 8: ...es USB PD to provide the cable s characteristics End Of Packet EOP K code marker used to delineate the end of a packet I2 C Inter integrated circuit Packet An entire unit of PD communication including...

Page 9: ...or a hub that connects to a host or a hub DFP USB Universal Serial Bus USB IF Universal Serial Bus Implementers Forum Vendor Defined Message VDM PD Data Message defined for vendor standards usage The...

Page 10: ...e Installation package CY4502Setup exe contains the kit hardware files documents guides and cc_flash utility Double click on CY4502Setup exe to start the installer Click Next on the first screen to st...

Page 11: ...tion Wizard 3 Accept the license agreement for the software components and click Next The kit will now install on your machine Figure 2 3 Figure 2 3 Installation Progress 4 When installation is comple...

Page 12: ...3 Install Software When installing the CY4502 DVK the installer checks if the required software is installed in the system If the required applications are not installed then it installs them as prere...

Page 13: ...ndicate the powered chip The two CYPD2103 devices in the CY4502 board are shipped with factory installed firmware that demonstrates the functionality of CCG2 controllers in EMCA USB PD Type C cables T...

Page 14: ...position for the two chip EMCA solution with both chips powered shown in Figure 3 9 Note The configuration with both chips powered will work in this DVK irrespective of which Type C plug connector J1...

Page 15: ...pers to enable SOP response of U2 CYPD2103 14LHXIT Short Enables SOP response by pulling GPIO D3 low CYPD2103 firmware is configured to detect the presence of the VCONN supply in the VCONN1 VCONN2 pin...

Page 16: ...IO SWD_ CLK E2 D1 I2C_0 _SCL I2C_0 _SDA A3 A2 B4 CC1 GPIO GPIO D3 C2 CC2 A4 E4 VCONN1 C4 VCONN2 VDDIO E1 RD1 B3 VSS D4 GPIO D2 GPIO B2 GPIO C3 0 1uF 1uF VDDIO 4 7 k This EMCA solution contains a CCG2...

Page 17: ...red VCONN1 VBUS CC Type C Plug Type C Plug VCONN2 GND SuperSpeed and HighSpeed Lines CCG2 CYPD2103 20FNXIT VDDD E3 A1 VCCD VSS C1 XRES B1 SWD_ IO SWD_ CLK E2 D1 I2C_0 _SCL I2C_0 _SDA A3 A2 B4 CC1 GPIO...

Page 18: ...wo Chip EMCA Application Diagram Both Chips Powered VCONN1 VBUS CC Type C Plug Type C Plug VCONN2 GND SuperSpeed and Hi Speed Lines CCG2 CYPD2103 20FNXIT VDDD E3 A1 VCCD VSS C1 XRES B1 SWD_ IO SWD_ CL...

Page 19: ...oller s and the CY4502 board are powered Table 3 2 LED indicators in CY4502 CY4502 Configuration Reference Connector to Host LED Description CCG2 Single Chip EMCA Application Section 3 3 J1 LED1 CCG2...

Page 20: ...Remove zero ohm resistors R1248 R1249 on the CCG1 Host Demo board 5 Ensure that the CCG1 Client Demo board Figure 3 11 has the jumper settings listed in Table 3 4 Figure 3 11 CCG1 Client Demo board T...

Page 21: ...and check the data integrity 3 7 Programming the CCG2 Device CCG2 devices can be upgraded to keep pace with USB IF specification changes The on chip 32 KB flash can be programmed using the serial wire...

Page 22: ...and Debug Kit from the Cypress webpage To use PSoC Programmer follow these steps 1 Start PSoC Programmer from Start All Programs Cypress PSoC Programmer 2 Connect one end of the USB cable to the Mini...

Page 23: ...rogram the hex file onto the chip 10 When the file is successfully programmed Programming Succeeded appears in the Actions window 3 7 2 Programming the CCG2 Device Using a CCG1 Host Demo Kit over the...

Page 24: ...s after this procedure is over you will need to restore the board to its normal host functionality Contact Cypress for more details 1 Program the CCG1 chip in the CCG1 Host Demo board with the firmwar...

Page 25: ...Demo board 6 The CC_Flash Utility can be found at the location Install Directory CY4502 CCG2 DVK version Util or can be downloaded CC_Flash Utility zip from this Cypress webpage 7 Launch the Command l...

Page 26: ...Application configuration section 3 3 only the U1 firmware can be upgraded by connecting CY4502 board using Type C plug J1 or J2 to the CCG1 Host Demo board connector J15 using the following command c...

Page 27: ...ck OK to close the window Upon closing the window Click the Utilities tab and then click the Upgrade Firmware button On successful upgrade the Action and Results window displays the firmware update me...

Page 28: ...Cypress USB Serial SDK for 64 bit operating system 2 Go to Select Target tab USB SERIAL device will be listed in the Select Device drop down list Click Connect 3 Navigate to SCB tab Choose Mode as I2...

Page 29: ...own in Figure 4 1 It covers the following topics CCG2 controllers Type C plugs SWD connectors Headers Figure 4 1 CY4502 board Hardware Block Diagram SWD Connector for programming CCG2 LEDs CCG signal...

Page 30: ...pers to select the responsiveness to SOP packets for U1 U2 respectively J1 J2 USB Type C plugs J3 J4 SWD connectors J9 20 pin header Not mounted on the DVK 4 2 CCG2 Controller CY4502 board consist of...

Page 31: ...SS_TX_P SS_RX_P and SS_RX_M USB 2 0 pins D and D cable power signals VBUS and GND sideband use SBU signals SBU1 SBU2 and the configuration channel CC VCONN that are available on the J1 and J2 USB Type...

Page 32: ...tails on Alternate mode In Alternate mode activity on the SBU lines does not interfere with USB PD BMC communications SBU signals are not implemented for USB 3 0 USB2 0 only cable applications Table 4...

Page 33: ...tional data bus used to transmit or receive data from the CCG2 device as shown in Figure 4 6 The RESET signal is used to pull down the RESET pin of the CCG2 device to bring it into the Programming mod...

Page 34: ...ings are in accordance with those in CCG2 Two Chip EMCA Application both chips powered LED1 does not glow when connected in one chip two chip configuration Corrupted flash or blank flash of CCG2 contr...

Page 35: ...CY4502 EZ PD CCG2 Development Kit Guide Doc No 001 96601 Rev B 35 Appendix B PCB Layout B 1 Top Layer B 2 Bottom Layer...

Page 36: ...Appendix B PCB Layout CY4502 EZ PD CCG2 Development Kit Guide Doc No 001 96601 Rev B 36 B 3 Ground Layer 1 B 4 Ground Layer 2...

Page 37: ...Appendix B PCB Layout CY4502 EZ PD CCG2 Development Kit Guide Doc No 001 96601 Rev B 37 B 5 Power Layer 1 B 6 Power Layer 2...

Page 38: ...ory Document Title CY4502 EZ PD CCG2 Development Kit Guide Document Number 001 96601 Revisio n Issue Date Origin of Change Description of Change 04 14 2015 GAYA Initial version of kit guide A 04 17 20...

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