Hardware
CY4502 EZ-
PD™ CCG2 Development Kit Guide, Doc. No. 001-96601 Rev. *B
33
4.4 SWD Connector
CY4502 board consist of two SWD connectors for programming and they are
J3, J4: SWD connectors
The SWD connectors are used to program and debug the CCG2 devices. SWD_CLK is the clock coming from the master
(programmer), and SWD_IO is the bidirectional data bus used to transmit or receive data from the CCG2 device, as shown
in
. The RESET signal is used to pull down the RESET pin of the CCG2 device to bring it into the Programming
mode.
Figure 4-6. SWD Connectors for Programming
4.5 20-pin Header
CY4502 board consist of one 20-pin header
J9: 20-pin header (Not mounted on the DVK)
The CCG2 GPIOs and I
2
C lines are exposed on the 20-pin header (
). The R
D
line from U1, VCONN and CC lines
are also accessible as test points for debugging.
Figure 4-7. 20-Pin Header
