CY8CKIT-038 PSoC 4200 Family Processor Module Kit Guide, Doc. # 001-85916 Rev. **
17
4.
Hardware
4.1
System Block Diagram
Figure 4-1. PSoC 4200 Family Block Diagram
Features
■
48-MHz Cortex-M0 CPU (0.9 DMIPS/MHz)
■
32-KB flash and 4-KB SRAM
■
Programmable logic: Four Universal Digital Blocks
■
Analog blocks: 12-bit 1-MSPS SAR ADC with Sample and Hold and a Programmable Sequencer,
a Continuous Time Block with two opamps with a Comparator mode, a Temperature Sensor, and
two low-power comparators
■
Fixed function digital blocks: Two combination UART/SPI/I2C (one function at a time) Serial Com-
munication Blocks (SCB). Four 16-bit Counter/Timer/PWMs with centre-aligned capability.
Peripherals
PSoC 4200
Family Device
32-bit
AHB-Lite
CPU & Memory
Peripheral Interconnect (MMIO)
System Interconnect (Single Layer AHB)
SRAM
4 kB
SRAM Controller
SWD/TC
NVIC, IRQMX
Cortex
M0
48 MHz
FAST MUL
SROM
4 kB
ROM Controller
FLASH
32 kB
Read Accelerator
SPCIF
Programmable
Digital
UDB
UDB
UDB
UDB
x4
Programmable I/O
LCD
SMX
SAR
(12-bit)
x1
Programmable
Analog
36x
G
P
IO
I/O Pins (Analog, Digital, Special, ESD)
2
x
LP
Com
p
a
rat
or
C
a
ps
ens
e
High Speed I/O Matrix
2x OpAmp
x1
CTBm
4x
T
C
PWM
2x
SC
B-
I2
C/SPI/
U
A
R
T
PC
L
K
Port Interface & Digital System Interconnect (DSI)
System Resources
Power
Clock
WDT
ILO
Reset
Clock Control
DFT Logic
Test
IMO
DFT Analog
Sleep Control
PWRSYS
REF
POR
LVD
NVLatches
BOD
WIC
Reset Control
XRES
Deep Sleep
Hibernate
Active/Sleep
Summary of Contents for CY8CKIT-038
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Page 22: ...22 CY8CKIT 038 PSoC 4200 Family Processor Module Kit Guide Doc 001 85916 Rev Example Projects ...
Page 38: ...38 CY8CKIT 038 PSoC 4200 Family Processor Module Kit Guide Doc 001 85916 Rev Example Projects ...
