CY62167EV18 MoBL
®
16 Mbit (1M x 16) Static RAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05447 Rev. *G
Revised March 13, 2009
Features
■
Very high speed: 55 ns
■
Wide voltage range: 1.65V to 2.25V
■
Ultra low standby power
❐
Typical standby current: 1.5
μ
A
❐
Maximum standby current: 12
μ
A
■
Ultra low active power
❐
Typical active current: 2.2 mA at f = 1 MHz
■
Easy memory expansion with CE
1
, CE
2
, and OE features
■
Automatic power down when deselected
■
CMOS for optimum speed and power
■
Offered in Pb-free 48-ball VFBGA packages
Functional Description
The CY62167EV18 is a high performance CMOS static RAM
organized as 1M words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life
™
(MoBL
®
) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that reduces power consumption
by 99 percent when addresses are not toggling. Place the device
into standby mode when deselected (CE
1
HIGH or CE
2
LOW or
both BHE and BLE are HIGH). The input and output pins (I/O
0
through I/O
15
) are placed in a high impedance state when: the
device is deselected (CE
1
HIGH or CE
2
LOW); outputs are
disabled (OE HIGH); both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH); and a write operation is
in progress (CE
1
LOW, CE
2
HIGH and WE LOW).
To write to the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
) is
written into the location specified on the address pins (A
0
through
A
19
). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O
8
through I/O
15
) is written into the location specified on the
address pins (A
0
through A
19
).
To read from the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O
8
to I/O
15
. See the
Truth Table on page
9
for a complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note
AN1064, SRAM System Guidelines
.
Power Down
Circuit
BHE
BLE
CE
2
CE
1
1M × 16
RAM ARRAY
IO
0
–IO
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
IO
8
–IO
15
WE
BLE
BHE
A
16
A
0
A
1
A
17
A
9
A
18
A
10
CE
2
CE
1
A
19
Logic Block Diagram
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