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CY62167EV18 MoBL

®

Document #: 38-05447 Rev. *G

Page 8 of 13

Figure 7

 

shows

 

CE

1

 or CE

2

 controlled write cycle waveforms.

[17, 21, 22]

Figure 7.  Write Cycle No. 2

Figure 8

 shows WE controlled, OE LOW write cycle waveforms.

[22]

Figure 8.  Write Cycle No. 3

Switching Waveforms

 (continued)

t

HD

t

SD

t

PWE

t

HA

t

AW

t

SCE

t

WC

t

HZOE

VALID DATA

t

BW

t

SA

NOTE 23

CE

1

ADDRESS

CE

2

WE

DATA I/O

OE

BHE/BLE

VALID DATA

t

HD

t

SD

t

LZWE

t

PWE

t

SA

t

HA

t

AW

t

SCE

t

WC

t

HZWE

t

BW

NOTE 23

CE

1

ADDRESS

CE

2

WE

DATA I/O

BHE/BLE

[+] Feedback 

Summary of Contents for CY62167EV18

Page 1: ...when the device is deselected CE1HIGH or CE2 LOW outputs are disabled OE HIGH both Byte High Enable and Byte Low Enable are disabled BHE BLE HIGH and a write operation is in progress CE1 LOW CE2 HIGH and WE LOW To write to the device take Chip Enables CE1 LOW and CE2 HIGH and Write Enable WE input LOW If Byte Low Enable BLE is LOW then data from I O pins I O0 through I O7 is written into the locat...

Page 2: ...4 IO15 VSS A9 A8 OE Vss A7 IO0 BHE CE2 A17 A2 A1 BLE VCC IO2 IO1 IO3 IO4 IO5 IO6 IO7 A15 A14 A13 A12 A19 A18 NC 3 2 6 5 4 1 D E B A C F G H A16 NC Vcc Notes 1 The information related to 6 x 7 x 1 mm VFBGA package is preliminary 2 NC pins are not connected on the die 3 Ball H6 for the VFBGA package can be used to upgrade to a 32M density 4 Typical values are included for reference only and are not ...

Page 3: ...65V to 2 25V 0 2 0 4 V IIX Input Leakage Current GND VI VCC 1 1 μA IOZ Output Leakage Current GND VO VCC Output Disabled 1 1 μA ICC VCC Operating Supply Current f fmax 1 tRC VCC VCC max IOUT 0 mA CMOS levels 25 30 mA f 1 MHz 2 2 4 0 mA ISB1 Automatic CE Power Down Current CMOS Inputs CE1 VCC 0 2V or CE2 0 2V VIN VCC 0 2V VIN 0 2V f fmax Address and Data Only f 0 OE WE BHE and BLE VCC VCC max 1 5 1...

Page 4: ... for Data Retention 1 0 V ICCDR 9 Data Retention Current VCC 1 0V CE1 VCC 0 2V CE2 0 2V VIN VCC 0 2V or VIN 0 2V 10 μA tCDR 10 Chip Deselect to Data Retention Time 0 ns tR 11 Operation Recovery Time tRC ns Figure 3 Data Retention Waveform VCC VCC OUTPUT R2 30 pF INCLUDING JIG AND SCOPE GND 90 10 90 10 Rise Time 1 V ns Fall Time 1 V ns OUTPUT V Equivalent to THÉVENIN EQUIVALENT ALL INPUT PULSES RTH...

Page 5: ...to Write End 25 ns tHD Data Hold from Write End 0 ns tHZWE WE LOW to High Z 15 16 20 ns tLZWE WE HIGH to Low Z 15 10 ns Notes 13 Test conditions for all parameters other than tri state parameters are based on signal transition time of 1V ns timing reference levels of VCC typ 2 input pulse levels of 0 to VCC typ and output loading of the specified IOL IOH as shown in AC Test Loads and Waveforms on ...

Page 6: ... PREVIOUS DATA VALID DATA VALID RC tAA tOHA tRC ADDRESS DATA OUT 50 50 DATA VALID tRC tACE tDOE tLZOE tLZCE tPU HIGH IMPEDANCE tHZOE tPD tHZBE tLZBE tHZCE tDBE OE CE1 ADDRESS CE2 BHE BLE DATA OUT VCC SUPPLY CURRENT HIGH ICC ISB IMPEDANCE Notes 18 The device is continuously selected OE CE1 VIL BHE BLE or both VIL and CE2 VIH 19 WE is HIGH for read cycle 20 Address valid before or similar to CE1 BHE...

Page 7: ...orms continued tHD tSD tPWE tSA tHA tAW tSCE tWC tHZOE VALID DATA tBW NOTE 23 CE1 ADDRESS CE2 WE DATA I O OE BHE BLE Notes 21 Data IO is high impedance if OE VIH 22 If CE1 goes HIGH and CE2 goes LOW simultaneously with WE VIH the output remains in a high impedance state 23 During this period the IOs are in output state Do not apply input signals Feedback ...

Page 8: ...cle No 2 Figure 8 shows WE controlled OE LOW write cycle waveforms 22 Figure 8 Write Cycle No 3 Switching Waveforms continued tHD tSD tPWE tHA tAW tSCE tWC tHZOE VALID DATA tBW tSA NOTE 23 CE1 ADDRESS CE2 WE DATA I O OE BHE BLE VALID DATA tHD tSD tLZWE tPWE tSA tHA tAW tSCE tWC tHZWE tBW NOTE 23 CE1 ADDRESS CE2 WE DATA I O BHE BLE Feedback ...

Page 9: ...Read Active ICC L H H L H L Data Out I O0 I O7 High Z I O8 I O15 Read Active ICC L H H L L H High Z I O0 I O7 Data Out I O8 I O15 Read Active ICC L H H H L H High Z Output Disabled Active ICC L H H H H L High Z Output Disabled Active ICC L H H H L L High Z Output Disabled Active ICC L H L X L L Data In I O0 I O15 Write Active ICC L H L X H L Data In I O0 I O7 High Z I O8 I O15 Write Active ICC L H...

Page 10: ...297 48 ball VFBGA 6 7 1 mm Pb free Industrial CY62167EV18LL 55BVI 51 85150 48 ball VFBGA 6 8 1 mm CY62167EV18LL 55BVXI 48 ball VFBGA 6 8 1 mm Pb free CY62167EV30LL 45BVI 5 51 85150 48 ball VFBGA 6 8 1 mm Package Diagram Figure 10 48 Ball VFBGA 6 x 7 x 1 mm 001 13297 NOTES 1 ALL DIMENSION ARE IN MM MAX MIN 2 JEDEC REFERENCE MO 216 3 PACKAGE WEIGHT 0 03g 001 13297 A Feedback ...

Page 11: ...ram A 1 A1 CORNER 0 75 0 75 Ø0 30 0 05 48X Ø0 25 M C A B Ø0 05 M C B A 0 15 4X 0 21 0 05 1 00 MAX C SEATING PLANE 0 55 MAX 0 25 C 0 10 C A1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 3 75 5 25 B C D E F G H 6 5 4 6 5 2 3 1 D H F G E C B A 6 00 0 10 8 00 0 10 A 8 00 0 10 6 00 0 10 B 1 875 2 625 0 26 MAX 51 85150 D Feedback ...

Page 12: ... tHZWE from 15 ns to 18 ns Changed tSCE tAW and tBW from 40 ns to 35 ns Changed tPE from 30 ns to 35 ns Changed tSD from 20 ns to 25 ns Updated 48 ball FBGA Package Information Updated the Ordering Information table B 469182 NSI See ECN Minor Change Moved to external web C 619122 NXR See ECN Replaced 45 ns speed bin with 55 ns speed bin D 1130323 VKN See ECN Converted from preliminary to final Add...

Page 13: ... firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WIT...

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