Cypress CapSense CY8CMBR2044, Design Manual

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Electrical and Mechanical Design Considerations
AN66308 - CY8CMBR2044 CapSense® Design Guide, Doc. No. 001-66308 Rev. *F 32
Electromagnetic Compatibility (EMC) Considerations
Radiated Interference
Radiated electrical energy can influence system measurements and potentially influence the operation of the
processor core. The interference enters the CY8CMBR2044 chip at the PCB level, through CapSense button traces
and any other digital or analog inputs. The Layout guidelines for minimizing the effects of RF interference follow:

Ground Plane : provide a ground plane on the PCB

Series Resistor : place series resistors within 10 mm of the CapSense controller pins
o
The recommended series resistance for CapSense input lines is 560
Ω

Trace Length : Minimize trace length whenever possible

Current Loop Area : Minimize the return path for current. To reduce the impact of parasitic capacitance,
hatched ground is given within 1 cm of the buttons and traces, instead of solid fill.

RF Source Location : Partition systems with noise sources, such as LCD inverters and switched-mode
power supplies (SMPS), to keep the interference separated from CapSense inputs. Shielding the power
supply is another common technique to prevent interference.
Conducted Immunity and Emissions
Noise entering a system through interconnections with other systems is referred to as conducted noise. Examples
include power and communication lines. Because the CapSense controllers are low-power devices, you must avoid
conducted emissions. The following guidelines will help to reduce conducted emission and immunity:

Use decoupling capacitors.

Add a bidirectional filter on the input to the system power supply. This is effective for both conducted
emissions and immunity. A pi-filter can prevent power supply noise from effecting sensitive parts and also
prevent the switching noise of the part itself from coupling back onto the power planes
.

If the CapSense controller PCB is connected to the power supply by a cable, minimize the cable length and
consider using a shielded cable.

To filter out high-frequency noise, place a ferrite bead around power supply or communication lines.
PCB Layout Guidelines
The Design Toolbox will help you design a robust and reliable CY8CMBR2044 CapSense PCB layout, as discussed
in Section 0
If your design uses the GPOs to sink current to the CapSense controller, and there is a lot of noise in the CapSense
system, use series resistors on all of the GPOs to limit sink current. Sink current limit is determined by the maximum
button C
P
in your design at 5 V, as show in Table 4-3 .
Table 4-3. GPO Sink Current Limit for Low Output Voltage
Button C
P
Range Sink Current Limit per GPO Sink Current Limit for Device
5 pF
≤ C
P
≤ 12 pF
25 mA 120 mA
12 pF
≤ C
P
≤ 21 pF
20 mA 20 mA
21 pF
≤ C
P
≤ 40 pF
6 mA 6 mA
Detailed PCB layout guidelines are available in Getting Started with CapSense , Section 3.7.