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Design Considerations
AN64846 - Getting Started with CapSense
®
Doc. No. 001-64846 Rev. *X
71
Figure 3-47. Not Recommended: C
MOD
/R
B
and LED Pins in Proximity
CapSense Controller
VDD
PWM or other
Non- CapSense traces
Communication
traces
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Note that in PSoC1, using the P1.0 and P1.1 pins for LEDs or for communication purposes is not recommended. This
is because, P1.0 and P1.1 pins are programming lines and upon power up, there will be a low pulse on the P1.0 and
P1.1 pins. For further clarity, you can also refer to the individual device design guides webpage having the sample
schematics of all the CapSense devices:
For similar guidelines on PSoC3, PSoC4 and PSoC5LP, refer to the respective
3.8 PCB Layout Guidelines
In the typical CapSense application, the capacitive sensors are formed by the traces of a printed circuit board (PCB) or
flex circuit. Following CapSense layout best practices will help your design achieve higher noise immunity, lower C
P
,
and higher signal-to-noise ratio (SNR). The CapSense signal drops off at high C
P
levels due to drive limits of the internal
current sources that are part of the CapSense circuitry. The long time constants associated with high C
P
are another
reason to avoid high C
P.
3.8.1 Parasitic Capacitance, C
P
The main components of C
P
are trace capacitance and sensor capacitance. C
P
is a nonlinear function of sensor
diameter, trace length, trace width, and the annular gap. There is no simple relation between C
P
and PCB layout
features, but here are the general trends. An increase in sensor size, an increase in trace length and width, and a
decrease in the annular gap all cause an increase in C
P
. One way to reduce C
P
is to increase the air gap between the
sensor and ground. Unfortunately, widening the gap between sensor and ground will decrease noise immunity.
3.8.2 Board Layers
Most applications use a two-layer board with sensor pads and a hatched ground plane on the top side and all other
components on the bottom side. The two-layer stack-up is shown in
. In applications where board space is
limited or the CapSense circuit is part of a PCB design containing complex circuitry, four-layer PCBs are used.