STK12C68-5 (SMD5962-94599)
Document Number: 001-51026 Rev. **
Page 9 of 18
AC Switching Characteristics
SRAM Read Cycle
Parameter
Description
35 ns
55 ns
Unit
Min
Max
Min
Max
Cypress
Parameter
Alt
t
ACE
t
ELQV
Chip Enable Access Time
35
55
ns
t
RC
[7]
t
AVAV,
t
ELEH
Read Cycle Time
35
55
ns
t
AA
[8]
t
AVQV
Address Access Time
35
55
ns
t
DOE
t
GLQV
Output Enable to Data Valid
15
35
ns
t
OHA
[8]
t
AXQX
Output Hold After Address Change
5
5
ns
t
LZCE
[9]
t
ELQX
Chip Enable to Output Active
5
5
ns
t
HZCE
[9]
t
EHQZ
Chip Disable to Output Inactive
10
12
ns
t
LZOE
[9]
t
GLQX
Output Enable to Output Active
0
0
ns
t
HZOE
[9]
t
GHQZ
Output Disable to Output Inactive
10
12
ns
t
PU
[6]
t
ELICCH
Chip Enable to Power Active
0
0
ns
t
PD
[6]
t
EHICCL
Chip Disable to Power Standby
35
55
ns
Switching Waveforms
Figure 8. SRAM Read Cycle 1: Address Controlled
[7, 8]
Figure 9. SRAM Read Cycle 2: CE and OE Controlled
[7]
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Notes
7. WE and HSB must be High during SRAM Read cycles.
8. Device is continuously selected with CE and OE both Low.
9. Measured ±200 mV from steady state output voltage.
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