Cypress Semiconductor SMD5962-94599 Page 14 Specification Sheet Download

Page: 14 / 18

STK12C68-5 (SMD5962-94599)

Document Number: 001-51026 Rev. **

Page 14 of 18

Speed:
35 - 35 ns
55 - 55 ns

Package:
C = Ceramic 28-pin 300 mil DIP (gold lead finish)

Part Numbering Nomenclature

STK12C68 - 5 C 35 M

Temperature Range:

M - Military (-55 to 125°C)

L = Ceramic 28-pin LLC

= Ceramic 28-pin 300 mil DIP (Solder dip finish)

Retention / Endurance

5 = Military (10 years or 10

cycles)

Case Outline

X = Ceramic 28-pin 300 mil DIP
Y = Ceramic 28-pin LLC

Device Class Indicator - Class M

SMD5962 - 94599 01 MX X

Lead Finish

A = Solder DIP lead finish

Device Type:

01 = 55 ns
03 = 35 ns

C = Gold lead DIP finish
X = Lead finish “A” or “C” is acceptable

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Summary of Contents for SMD5962-94599

Page 1: ...ith a nonvol atile element in each memory cell The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides unlimited read and write cycles while independent nonvolatile data resides in the highly reliable QuantumTrap cell Data transfers from the SRAM to the nonvolatile elements the STORE operation takes place automat...

Page 2: ...Output Enable Active LOW The active LOW OE input enables the data output buffers during read cycles Deasserting OE HIGH causes the IO pins to tri state VSS Ground Ground for the Device The device is connected to ground of the system VCC Power Supply Power Supply Inputs to the Device HSB Input or Output Hardware Store Busy HSB When LOW this output indicates a Hardware Store is in progress When pull...

Page 3: ... controlled Write Keep OE HIGH during the entire Write cycle to avoid data bus contention on common IO lines If OE is left LOW internal circuitry turns off the output buffers tHZWE after WE goes LOW AutoStore Operation The STK12C68 5 stores data to nvSRAM using one of three storage operations 1 Hardware store activated by HSB 2 Software store activated by an address sequence 3 AutoStore on device ...

Page 4: ...ected Hardware RECALL Power Up During power up or after any low power condition VCC VRESET an internal RECALL request is latched When VCC once again exceeds the sense voltage of VSWITCH a RECALL cycle is automatically initiated and takes tHRECALL to complete If the STK12C68 5 is in a Write state at the end of power up RECALL the SRAM data is corrupted To help avoid this situation a 10 Kohm resisto...

Page 5: ...ge condi tions When VCAP VSWITCH all externally initiated STORE operations and SRAM Writes are inhibited AutoStore can be completely disabled by tying VCC to ground and applying 5V to VCAP This is the AutoStore Inhibit mode in this mode STOREs are only initiated by explicit request using either the software sequence or the HSB pin Low Average Active Power CMOS technology provides the STK12C68 5 th...

Page 6: ...ection routines and so on The Vcap value specified in this data sheet includes a minimum and a maximum value size The best practice is to meet this requirement and not exceed the maximum Vcap value because the higher inrush currents may reduce the reliability of the internal pass transistor Customers who want to use a larger Vcap value to make sure there is extra store charge must discuss their Vc...

Page 7: ... 0 2V All other inputs cycling Dependent on output loading and cycle rate Values obtained without output loads 10 mA ICC4 Average VCAP Current during AutoStore Cycle All Inputs Do Not Care VCC Max Average current for duration tSTORE 2 mA ISB1 5 VCC Standby Current Standby Cycling TTL Input Levels tRC 35 ns CE VIH tRC 55 ns CE VIH 24 19 mA mA ISB2 5 VCC Standby Current CE VCC 0 2V All others VIN 0 ...

Page 8: ...g table the thermal resistance parameters are listed 6 Parameter Description Test Conditions 28 CDIP 28 LCC Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 TBD TBD C W ΘJC Thermal Resistance Junction to Case TBD TBD C W Figure 7 AC Test Loads AC Test Conditions 5 0V Output 30 pF R1 963Ω R2 51...

Page 9: ... Active 5 5 ns tHZCE 9 tEHQZ Chip Disable to Output Inactive 10 12 ns tLZOE 9 tGLQX Output Enable to Output Active 0 0 ns tHZOE 9 tGHQZ Output Disable to Output Inactive 10 12 ns tPU 6 tELICCH Chip Enable to Power Active 0 0 ns tPD 6 tEHICCL Chip Disable to Power Standby 35 55 ns Switching Waveforms Figure 8 SRAM Read Cycle 1 Address Controlled 7 8 Figure 9 SRAM Read Cycle 2 CE and OE Controlled 7...

Page 10: ...e 0 0 ns tHA tWHAX tEHAX Address Hold After End of Write 0 0 ns tHZWE 9 10 tWLQZ Write Enable to Output Disable 13 15 ns tLZWE 9 tWHQX Output Active After End of Write 5 5 ns Switching Waveforms Figure 10 SRAM Write Cycle 1 WE Controlled 11 12 Figure 11 SRAM Write Cycle 2 CE Controlled 11 12 tWC tSCE tHA tAW tSA tPWE tSD tHD tHZWE tLZWE ADDRESS CE WE DATA IN DATA OUT DATA VALID HIGH IMPEDANCE PREV...

Page 11: ... Trigger Level 4 0 4 5 V VRESET Low Voltage Reset Level 3 9 V tVCCRISE VCC Rise Time 150 μs tVSBL 11 Low Voltage Trigger VSWITCH to HSB Low 300 ns Switching Waveform Figure 12 AutoStore Power Up RECALL WE Notes 13 tHRECALL starts from the time VCC rises above VSWITCH 14 CE and OE low for output behavior 15 CE and OE low and WE high for output behavior 16 HSB is asserted low for 1us when VCAP drops...

Page 12: ...0 ns tHACE 17 tELAX Address Hold Time 20 20 ns tRECALL RECALL Duration 20 20 μs Switching Waveform Figure 13 CE Controlled Software STORE RECALL Cycle 18 tRC tRC tSA tSCE tHACE tSTORE tRECALL DATA VALID DATA VALID 6 S S E R D D A 1 S S E R D D A HIGH IMPEDANCE ADDRESS CE OE DQ DATA Notes 17 The software sequence is clocked on the falling edge of CE without involving OE double clocking aborts the s...

Page 13: ...t Min Max tSTORE 9 14 tHLHZ STORE Cycle Duration 10 ms tDHSB 14 19 tRECOVER tHHQX Hardware STORE High to Inhibit Off 700 ns tPHSB tHLHX Hardware STORE Pulse Width 15 ns tHLBL Hardware STORE Low to STORE Busy 300 ns Switching Waveform Figure 14 Hardware STORE Cycle Note 19 tDHSB is only applicable after tSTORE is complete Feedback ...

Page 14: ...re Range M Military 55 to 125 C K L Ceramic 28 pin LLC Ceramic 28 pin 300 mil DIP Solder dip finish Retention Endurance 5 Military 10 years or 105 cycles Case Outline X Ceramic 28 pin 300 mil DIP Y Ceramic 28 pin LLC Device Class Indicator Class M SMD5962 94599 01 MX X Lead Finish A Solder DIP lead finish Device Type 01 55 ns 03 35 ns C Gold lead DIP finish X Lead finish A or C is acceptable Feedb...

Page 15: ... 28 pin CDIP 300 mil Military STK12C68 5K35M 001 51695 28 pin CDIP 300 mil STK12C68 5L35M 001 51696 28 pin LCC 350 mil 55 STK12C68 5C55M 001 51695 28 pin CDIP 300 mil STK12C68 5K55M 001 51695 28 pin CDIP 300 mil STK12C68 5L55M 001 51696 28 pin LCC 350 mil The above table contains Final information Contact your local Cypress sales representative for availability of these parts Feedback ...

Page 16: ...STK12C68 5 SMD5962 94599 Document Number 001 51026 Rev Page 16 of 18 Package Diagrams Figure 15 28 Pin 300 Mil Side Braze DIL 001 51695 001 51695 Feedback ...

Page 17: ...ocument Number 001 51026 Rev Page 17 of 18 Figure 16 28 Pad 350 Mil LCC 001 51696 Package Diagrams continued 1 ALL DIMENSION ARE IN INCHES AND MILLIMETERS MIN MAX 2 JEDEC 95 OUTLINE MO 041 3 PACKAGE WEIGHT TBD 001 51696 Feedback ...

Page 18: ... specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS...

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