Document Number: 002-00856 Rev. *E
S29JL064J
18. Erase and Programming Performance
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0V V
CC
, 100,000 cycles; checkerboard data pattern.
2. Under worst case conditions of 90°C, V
CC
= 2.7V, 1,000,000 cycles.
3. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
4. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
for further information on
command definitions.
5. The device has a minimum program and erase cycle endurance of 100,000 cycles per sector.
19. Pin Capacitance
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25°C, f = 1.0 MHz.
Parameter
Typ
Unit
Comments
Sector Erase Time
0.5
5
sec
Excludes 00h programming
prior to erasure
Chip Erase Time
71
sec
Byte Program Time
6
80
µs
Excludes system level
overhead
Word Program Time
6
80
µs
Accelerated Byte/Word Program Time
4
70
µs
Parameter Symbol
Parameter Description
Test Setup
Max
Unit
C
IN
Input Capacitance (applies to A21-A0, DQ15-DQ0)
V
IN
= 0
8.5
pF
C
OUT
Output Capacitance (applies to DQ15-DQ0, RY/BY#)
V
OUT
= 0
5.5
pF
C
IN2
Control Pin Capacitance
(applies to CE#, WE#, OE#, WP#/ACC, RESET#, BYTE#)
V
IN
= 0
12
pF
