Cypress Semiconductor S29JL064J Manual Download Page 43

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Document Number: 002-00856 Rev. *E

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S29JL064J

17.2

Hardware Reset (RESET#)

Note:
Not 100% tested.

Figure 17.2

Reset Timings

Parameter

Description

All Speed Options

Unit

JEDEC

Std

Ready

RESET# Pin Low (During Embedded Algorithms) to Read
Mode

(See Note)

Max

µs

Ready

RESET# Pin Low (NOT During Embedded Algorithms) to
Read Mode

(See Note)

Max

500

RESET# Pulse Width

Min

500

Reset High Time Before Read

(See Note)

Min

RPD

RESET# Low to Standby Mode

Min

µs

RY/BY# Recovery Time

Min

RESET#

RY/BY#

Ready

Reset Timings NOT during Embedded Algorithms

Ready

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#

Summary of Contents for S29JL064J

Page 1: ...cycles per sector typical Data retention 20 years typical Software Features Supports Common Flash Memory Interface CFI Erase suspend erase resume Suspends erase operations to read data from or program...

Page 2: ...2 Reset Command 26 10 3 Autoselect Command Sequence 27 10 4 Enter Secured Silicon Region Exit Secured Silicon Region Command Sequence 27 10 5 Byte Word Program Command Sequence 27 10 6 Chip Erase Com...

Page 3: ...with the JEDEC 42 4 single power supply Flash command set standard Commands are written to the command register using standard microprocessor write timings Reading data out of the device is similar t...

Page 4: ...C 55 60 70 CE Access ns tCE 55 60 70 OE Access ns tOE 25 25 30 VCC VSS Bank 1 Address Bank 2 Address A21 A0 RESET WE CE BYTE DQ0 DQ15 WP ACC STATE CONTROL COMMAND REGISTER RY BY Bank 1 X Decoder OE BY...

Page 5: ...1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 A15 A18 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE RESET A21 WP ACC RY...

Page 6: ...nnected to the package connector The connection may be used by Spansion for test or other purposes and is not intended for connection to any host system signal Any DNU signal related function will be...

Page 7: ...Document Number 002 00856 Rev E Page 7 of 59 S29JL064J 6 Logic Symbol 22 16 or 8 DQ15 DQ0 A 1 A21 A0 CE OE WE RESET BYTE RY BY WP ACC...

Page 8: ...rial 40 C to 85 C Package Material Set F Pb free H Low halogen Pb free Package Type B Fine pitch Ball Grid Array FBGA Package T Thin Small Outline Package TSOP Standard Pinout Speed Option 55 55 ns 60...

Page 9: ...VIL sectors 0 1 140 and 141 remain protected If WP ACC VIH protection on sectors 0 1 140 and 141 depends on whether they were last protected or unprotected using the method described in Boot Sector S...

Page 10: ...r or the entire chip or suspending resuming the erase operation The device address space is divided into four banks A bank address is the address bits required to uniquely select a bank ICC2 in the DC...

Page 11: ...ic sleep mode current specification 8 7 RESET Hardware Reset Pin The RESET pin provides a hardware method of resetting the device to reading array data When the RESET pin is driven low for at least a...

Page 12: ...00C000h 00DFFFh 06000h 06FFFh SA7 0000000111 8 4 00E000h 00FFFFh 07000h 07FFFh SA8 0000001xxx 64 32 010000h 01FFFFh 08000h 0FFFFh SA9 0000010xxx 64 32 020000h 02FFFFh 10000h 17FFFh SA10 0000011xxx 64...

Page 13: ...0110xxx 64 32 260000h 26FFFFh 130000h 137FFFh SA46 0100111xxx 64 32 270000h 27FFFFh 138000h 13FFFFh SA47 0101000xxx 64 32 280000h 28FFFFh 140000h 147FFFh SA48 0101001xxx 64 32 290000h 29FFFFh 148000h...

Page 14: ...SA93 1010110xxx 64 32 560000h 56FFFFh 2B0000h 2B7FFFh SA94 1010111xxx 64 32 570000h 57FFFFh 2B8000h 2BFFFFh SA95 1011000xxx 64 32 580000h 58FFFFh 2C0000h 2C7FFFh SA96 1011001xxx 64 32 590000h 59FFFFh...

Page 15: ...64 32 7B0000h 7BFFFFh 3D8000h 3DFFFFh SA131 1111100xxx 64 32 7C0000h 7CFFFFh 3E0000h 3E7FFFh SA132 1111101xxx 64 32 7D0000h 7DFFFFh 3E8000h 3EFFFFh SA133 1111110xxx 64 32 7E0000h 7EFFFFh 3F0000h 3F7F...

Page 16: ...ut access to high voltage on the A9 pin The command sequence is illustrated in Table on page 31 Note that if a Bank Address BA on address bits A21 A20 and A19 is asserted during the third write cycle...

Page 17: ...0000001XXX 0000010XXX 0000011XXX 192 3x64 kbytes SA11 SA14 00001XXXXX 256 4x64 kbytes SA15 SA18 00010XXXXX 256 4x64 kbytes SA19 SA22 00011XXXXX 256 4x64 kbytes SA23 SA26 00100XXXXX 256 4x64 kbytes SA2...

Page 18: ...disables program and erase functions in sectors 0 1 140 and 141 independently of whether those sectors were protected or unprotected using the method described in Boot Sector Sector Block Protection a...

Page 19: ...rotected sectors can be programmed or erased by selecting the sector addresses Once VID is removed from the RESET pin all the previously protected sectors are protected again Figure 8 1 shows the algo...

Page 20: ...sector address with A6 1 A1 1 A0 0 Set up first sector address Wait 15 ms Verify Sector Unprotect Write 40h to sector address with A6 1 A1 1 A0 0 Read from sector address with A6 1 A1 1 A0 0 START PLS...

Page 21: ...addresses 000000h 000007h in word mode or 000000h 00000Fh in byte mode The secure ESN is programmed in the next 8 words at addresses 000008h 00000Fh or 000010h 00001Fh in byte mode The device is avail...

Page 22: ...VCC is greater than VLKO The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO 8 14 2 Write Pulse Glitch Protection Noise pulses...

Page 23: ...st write the reset command to return to reading array data For further information please refer to the CFI Specification and CFI Publication 100 Contact your local sales office for copies of these doc...

Page 24: ...Regions within device 2Dh 2Eh 2Fh 30h 5Ah 5Ch 5Eh 60h 0007h 0000h 0020h 0000h Erase Block Region 1 Information refer to the CFI specification or CFI publication 100 31h 32h 33h 34h 62h 64h 66h 68h 007...

Page 25: ...tor Protect Unprotect scheme 01 29F040 mode 02 29F016 mode 03 29F400 04 29LV800 mode 4Ah 94h 0077h Simultaneous Operation 00 Not Supported X Number of Sectors excluding Bank 1 4Bh 96h 0000h Burst Mode...

Page 26: ...26 for more information See Requirements for Reading Array Data on page 10 for more information Read Only Operations on page 42 provides the read parameters and Figure 17 1 on page 42 shows the timin...

Page 27: ...page 31 shows the address and data requirements for both command sequences See also Secured Silicon Region on page 21 for further information Note that the ACC function and unlock bypass modes are no...

Page 28: ...am and Unlock Bypass Reset commands are valid To exit the unlock bypass mode the system must issue the two cycle unlock bypass reset command sequence See Table on page 31 The device offers accelerated...

Page 29: ...trical erase The system is not required to provide any controls or timings during these operations After the command sequence is written a sector erase time out of 50 s occurs During the time out peri...

Page 30: ...red Silicon Region after an erase suspend as proper device functionality cannot be guaranteed Reading at any address within erase suspended sectors produces status information on DQ7 DQ0 The system ca...

Page 31: ...r to the erase suspend read mode if previously in Erase Suspend when a bank is in the autoselect mode or if DQ5 goes high while the bank is providing status information S29JL064J Command Definitions C...

Page 32: ...se algorithm is in progress or completed or whether a bank is in Erase Suspend Data Polling is valid after the rising edge of the final WE pulse in the command sequence During the Embedded Program alg...

Page 33: ...edded Algorithm is in progress or complete The RY BY status is valid after the rising edge of the final WE pulse in the command sequence Since RY BY is an open drain output several RY BY pins can be t...

Page 34: ...DQ6 toggles for approximately 3 ms then returns to reading array data If not all selected sectors are protected the Embedded Erase algorithm erases the unprotected sectors and ignores the selected se...

Page 35: ...cycles But DQ2 cannot distinguish whether the sector is actively erasing or is erase suspended DQ6 by comparison indicates whether the device is actively erasing or is in Erase Suspend but cannot dist...

Page 36: ...icates whether the program or erase time has exceeded a specified internal pulse count limit Under these conditions DQ5 produces a 1 indicating that the program or erase cycle was not successfully com...

Page 37: ...nput voltage on WP ACC is 9 5V which may overshoot to 12 0V for periods up to 20 ns 3 No more than one output may be shorted to ground at a time Duration of the short circuit should not be greater tha...

Page 38: ...VCC max RESET 12 5V 35 A ICC1 VCC Active Read Current Notes 1 2 CE VIL OE VIH Byte Mode 5 MHz 10 16 mA 1 MHz 2 4 CE VIL OE VIH Word Mode 5 MHz 10 16 1 MHz 2 4 ICC2 VCC Active Write Current Notes 2 3...

Page 39: ...Not 100 tested 14 2 Zero Power Flash Figure 14 1 ICC1 Current vs Time Showing Active and Automatic Sleep Currents Note Addresses are switching at 1 MHz VID Voltage for Autoselect and Temporary Sector...

Page 40: ...Specifications Test Condition 55 60 70 Unit Output Load Capacitance CL 30 100 pF Input Rise and Fall Times Note 1 5 ns Input Pulse Levels 0 0 or VCC V Input timing measurement reference levels 0 5 VC...

Page 41: ...Switching Waveforms Figure 16 1 Input Waveforms and Measurement Levels Waveform Inputs Outputs Steady Changing from H to L Changing from L to H Don t Care Any Change Permitted Changing State Unknown...

Page 42: ...td 55 60 70 Unit tAVAV tRC Read Cycle Time Note 1 Min 55 60 70 ns tAVQV tACC Address to Output Delay CE OE VIL Max 55 60 70 ns tELQV tCE Chip Enable to Output Delay OE VIL Max 55 60 70 ns tGLQV tOE Ou...

Page 43: ...ms to Read Mode See Note Max 35 s tReady RESET Pin Low NOT During Embedded Algorithms to Read Mode See Note Max 500 ns tRP RESET Pulse Width Min 500 ns tRH Reset High Time Before Read See Note Min 50...

Page 44: ...d 55 60 70 tELFL tELFH CE to BYTE Switching Low or High Max 5 ns tFLQZ BYTE Switching Low to Output High Z Max 16 ns tFHQV BYTE Switching High to Output Active Min 55 60 70 ns DQ15 Output Data Output...

Page 45: ...35 40 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write OE High to WE Low Min 0 ns tELWL tCS CE Setup Time M...

Page 46: ...ta at the program address 2 Illustration shows device in word mode Figure 17 6 Accelerated Program Timing Diagram OE WE CE VCC Data Addresses tDS tAH tDH tWP PD tWHWH1 tWC tAS tWPH tVCS 555h PA PA Rea...

Page 47: ...te Cycle Timings OE CE Addresses VCC WE Data 2AAh SA tAH tWP tWC tAS tWPH 555h for chip erase 10 for Chip Erase 30h tDS tVCS tCS tDH 55h tCH In Progress Complete tWHWH2 VA VA Erase Command Sequence la...

Page 48: ...ote VA Valid address not required for DQ6 Illustration shows first two status cycle after command sequence last status read cycle and array data read cycle WE CE OE High Z tOE High Z DQ7 DQ0 DQ6 RY BY...

Page 49: ...d Options JEDEC Std Unit tVIDR VID Rise and Fall Time See Note Min 500 ns tVHH VHH Rise and Fall Time See Note Min 250 ns tRSP RESET Setup Time for Temporary Sector Unprotect Min 4 s tRRB RESET Hold T...

Page 50: ...H Address Hold Time Min 30 35 40 ns tDVEH tDS Data Setup Time Min 30 35 40 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write OE High to WE Low Min 0 ns tWLEL tWS WE Setu...

Page 51: ...ress PD program data 3 DQ7 is the complement of the data written to the device DOUT is the data written to the device 4 Waveforms are for the word mode tGHEL tWS OE CE WE RESET tDS Data tAH Addresses...

Page 52: ...mation on command definitions 5 The device has a minimum program and erase cycle endurance of 100 000 cycles per sector 19 Pin Capacitance Notes 1 Sampled not 100 tested 2 Test conditions TA 25 C f 1...

Page 53: ...IE DOWN INK OR LASER MARK 4 TO BE DETERMINED AT THE SEATING PLANE C THE SEATING PLANE IS DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZO...

Page 54: ...ON OF THE CENTER SOLDER BALL IN THE OUTER ROW WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION RESPECTIVELY SD OR SE 0 000 WHEN THERE IS AN EVEN NUMBER OF...

Page 55: ...tion that It is not recommended to program the Secured Silicon Region after an erase suspend as proper device functionality cannot be guaranteed In Table 10 1 corrected the Secured Silicon Region Fact...

Page 56: ...dware Reset RESET Removed note to the Reset Timings figure clarifying that CE should only go low after RESET has gone high Erase and Programming Performance Updated Byte Program Time and Word Program...

Page 57: ...must write the reset command to return to reading array data Enter Secured Silicon Region Exit Secured Silicon Region Command Sequence Removed the incorrect generalizing statement that the Secured Sil...

Page 58: ...fying that CE should only go low after RESET has gone high C RYSU 08 24 2011 RESET Hardware Reset Pin Removed warning that keeping CE at VIL from power up through the first reset could cause erroneuou...

Page 59: ...pport of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representat...

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