Cypress Semiconductor MoBL-USB CY7C68053 Specification Sheet Download Page 21

CY7C68053

Document # 001-06120 Rev *F

Page 21 of 39

81

1 SP

Stack Pointer

D7

D6

D5

D4

D3

D2

D1

D0

00000111 RW

82

1 DPL0

Data Pointer 0 L

A7

A6

A5

A4

A3

A2

A1

A0

00000000 RW

83

1 DPH0

Data Pointer 0 H

A15

A14

A13

A12

A11

A10

A9

A8

00000000 RW

84

1 DPL1

[12]

Data Pointer 1 L

A7

A6

A5

A4

A3

A2

A1

A0

00000000 RW

85

1 DPH1

[12]

Data Pointer 1 H

A15

A14

A13

A12

A11

A10

A9

A8

00000000 RW

86

1 DPS

[12]

Data Pointer 0/1 select

0

0

0

0

0

0

0

SEL

00000000 RW

87

1 PCON

Power Control

SMOD0

x

1

1

x

x

x

IDLE

00110000 RW

88

1 TCON

Timer/Counter Control

(bit addressable)

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

00000000 RW

89

1 TMOD

Timer/Counter Mode 

Control

GATE

CT

M1

M0

GATE

CT

M1

M0

00000000 RW

8A

1 TL0

Timer 0 reload L

D7

D6

D5

D4

D3

D2

D1

D0

00000000 RW

8B

1 TL1

Timer 1 reload L

D7

D6

D5

D4

D3

D2

D1

D0

00000000 RW

8C

1 TH0

Timer 0 reload H

D15

D14

D13

D12

D11

D10

D9

D8

00000000 RW

8D

1 TH1

Timer 1 reload H

D15

D14

D13

D12

D11

D10

D9

D8

00000000 RW

8E

1 CKCON

[12]

Clock Control

x

x

T2M

T1M

T0M

MD2

MD1

MD0

00000001 RW

8F

1 Reserved

90

1 IOB

[12]

Port B (bit addressable)

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx RW

91

1 EXIF

[12]

External Interrupt Flag(s)

IE5

IE4

I²CINT

USBNT

1

0

0

0

00001000 RW

92

1 MPAGE

[12]

Upper Addr Byte of MOVX 

using @R0/@R1

A15

A14

A13

A12

A11

A10

A9

A8

00000000 RW

93

5 Reserved

98

1 SCON0

Serial Port 0 Control 

(bit addressable)

SM0_0

SM1_0

SM2_0

REN_0

TB8_0

RB8_0

TI_0

RI_0

00000000 RW

99

1 SBUF0

Serial Port 0 Data Buffer

D7

D6

D5

D4

D3

D2

D1

D0

00000000 RW

9A

1 AUTOPTRH1

[12]

Autopointer 1 Address H

A15

A14

A13

A12

A11

A10

A9

A8

00000000 RW

9B

1 AUTOPTRL1

[12]

Autopointer 1 Address L

A7

A6

A5

A4

A3

A2

A1

A0

00000000 RW

9C

1 Reserved

9D

1 AUTOPTRH2

[12]

Autopointer 2 Address H

A15

A14

A13

A12

A11

A10

A9

A8

00000000 RW

9E

1 AUTOPTRL2

[12]

Autopointer 2 Address L

A7

A6

A5

A4

A3

A2

A1

A0

00000000 RW

9F

1 Reserved

A0

1 IOC

[12]

Port C (bit addressable)

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx RW

A1

1 INT2CLR

[12]

Interrupt 2 clear

x

x

x

x

x

x

x

x

xxxxxxxx W

A2

1 Reserved

x

x

x

x

x

x

x

x

xxxxxxxx W

A3

5 Reserved

A8

1 IE

Interrupt Enable 

(bit addressable)

EA

ES1

ET2

ES0

ET1

EX1

ET0

EX0

00000000 RW

A9

1 Reserved

AA

1 EP2468STAT

[12]

Endpoint 2,4,6,8 status 

flags

EP8F

EP8E

EP6F

EP6E

EP4F

EP4E

EP2F

EP2E

01011010 R

AB

1 EP24FIFOFLGS

[12]

Endpoint 2,4 slave FIFO 

status flags

0

EP4PF

EP4EF

EP4FF

0

EP2PF

EP2EF

EP2FF

00100010 R

AC

1 EP68FIFOFLGS

[12]

Endpoint 6,8 slave FIFO 

status flags

0

EP8PF

EP8EF

EP8FF

0

EP6PF

EP6EF

EP6FF

01100110 R

AD

2 Reserved

AF

1 AUTOPTRSETUP

[12]

Autopointer 1&2 set-up

0

0

0

0

0

APTR2INC APTR1INC

APTREN

00000110 RW

B0

1 IOD

[12]

Port D (bit addressable)

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx RW

B1

1 IOE

[12]

Port E 

(NOT bit addressable)

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx RW

B2

1 OEA

[12]

Port A Output Enable

D7

D6

D5

D4

D3

D2

D1

D0

00000000 RW

B3

1 OEB

[12]

Port B Output Enable

D7

D6

D5

D4

D3

D2

D1

D0

00000000 RW

B4

1 OEC

[12]

Port C Output Enable

D7

D6

D5

D4

D3

D2

D1

D0

00000000 RW

B5

1 OED

[12]

Port D Output Enable

D7

D6

D5

D4

D3

D2

D1

D0

00000000 RW

B6

1 OEE

[12]

Port E Output Enable

D7

D6

D5

D4

D3

D2

D1

D0

00000000 RW

B7

1 Reserved

B8

1 IP

Interrupt Priority (bit ad-

dressable)

1

PS1

PT2

PS0

PT1

PX1

PT0

PX0

10000000 RW

B9

1 Reserved

BA

1 EP01STAT

[12]

Endpoint 0&1 Status

0

0

0

0

0

EP1INBSY

EP1OUTBSY

EP0BSY

00000000 R

BB

1 GPIFTRIG

[12, 10]

Endpoint 2,4,6,8 GPIF 

slave FIFO Trigger

DONE

0

0

0

0

RW

EP1

EP0

10000xxx brrrrbbb

BC

1 Reserved

BD

1 GPIFSGLDATH

[12]

GPIF Data H (16-bit mode 

only)

D15

D14

D13

D12

D11

D10

D9

D8

xxxxxxxx RW

BE

1 GPIFSGLDATLX

[12]

GPIF Data L w/Trigger

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx RW

BF

1 GPIFSGLDATL-

NOX

[12]

GPIF Data L w/No Trigger

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx R

C0

1 SCON1

[12]

Serial Port 1 Control (bit 

addressable)

SM0_1

SM1_1

SM2_1

REN_1

TB8_1

RB8_1

TI_1

RI_1

00000000 RW

C1

1 SBUF1

[12]

Serial Port 1 Data Buffer

D7

D6

D5

D4

D3

D2

D1

D0

00000000 RW

C2

6 Reserved

C8

1 T2CON

Timer/Counter 2 Control 

(bit addressable)

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

CT2

CPRL2

00000000 RW

Table 5-1.  FX2LP18 Register Summary 

 (continued)

Hex

Size Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

[+] Feedback 

Summary of Contents for MoBL-USB CY7C68053

Page 1: ...ocks per instruction cycle Three counter timers Expanded interrupt system Two data pointers 1 8V core operation 1 8V 3 3V IO operation Vectored USB interrupts and GPIF FIFO interrupts Separate data bu...

Page 2: ...s and documentation For more infor mation visit http www cypress com 3 0 Functional Overview The functionality of this chip is described in the sections below 3 1 USB Signaling Speed FX2LP18 operates...

Page 3: ...t the firmware sets DISCON to 1 To reconnect the firmware clears DISCON to 0 Before reconnecting the firmware sets or clears the RENUM bit to indicate whether the firmware or the Default USB Device ha...

Page 4: ...h speed operation 7 18 EP0ACK FX2LP18 ACK d the CONTROL Handshake 8 1C Reserved 9 20 EP0 IN EP0 IN ready to be loaded with data 10 24 EP0 OUT EP0 OUT has USB data 11 28 EP1 IN EP1 IN ready to be loade...

Page 5: ...3 WU2 pin The second wakeup pin WU2 can also be configured as a general purpose IO pin This allows a simple external R C network to be used as a periodic wakeup source Note that WAKEUP is by default a...

Page 6: ...ochronous EP4 and EP8 can be double buffered while EP2 and 6 can be double triple or quad buffered For high speed endpoint configuration options see Figure 3 5 3 12 3 Set up Data Buffer A separate 8 b...

Page 7: ...N EP1 OUT Figure 3 5 Endpoint Configuration 1024 1024 EP6 1024 512 512 EP8 512 512 EP6 512 512 512 512 EP2 512 512 EP4 512 512 EP2 512 512 EP4 512 512 EP2 512 512 EP4 512 512 EP2 512 512 512 512 EP2 5...

Page 8: ...clock with the IFCLKSRC bit Each endpoint can individually be selected for byte or word operation by an internal configuration bit and a Slave FIFO Output Enable signal SLOE enables data of the selec...

Page 9: ...The core has the ability to directly edit the data contents of the internal 16 kByte RAM and of the internal 512 byte scratch pad RAM via a vendor specific command This capability is normally used whe...

Page 10: ...he signals on the right edge of the diagram The 8051 selects the interface mode using the IFCONFIG 1 0 register bits Port mode is the power on default configuration Table 3 6 Strap Boot EEPROM Address...

Page 11: ...2 CY7C68053 56 pin VFBGA Pin Assignment Top view 1 2 3 4 5 6 7 8 A B C D E F G H 1A 2A 3A 4A 5A 6A 7A 8A 1B 2B 3B 4B 5B 6B 7B 8B 1C 2C 3C 4C 5C 6C 7C 8C 1D 2D 7D 8D 1E 2E 7E 8E 1F 2F 3F 4F 5F 6F 7F 8F...

Page 12: ...other clock source 2C XTALOUT Output N A Crystal Output Connect this signal to a 24 MHz parallel resonant funda mental mode crystal and load capacitor to GND If an external clock is used to drive XTAL...

Page 13: ...bus 4F PB1 or FD 1 I O Z I PB1 Multiplexed pin whose function is selected by the following bits IFCONFIG 1 0 PB1 is a bidirectional IO port pin FD 1 is the bidirectional FIFO GPIF data bus 4H PB2 or F...

Page 14: ...ted by the IFCONFIG 1 0 and EPxFIFOCFG 0 wordwide bits FD 15 is the bidirectional FIFO GPIF data bus 1A RDY0 or SLRD Input N A Multiplexed pin whose function is selected by the following bits IFCONFIG...

Page 15: ...quired 3G SDA OD Z Data for the I2 C interface Connect to VCC_IO or VCC with a 2 2K 10K pull up resistor An I2 C peripheral is required 5A VCC_IO Power N A VCC Connect this pin to 1 8V to 3 3V power s...

Page 16: ...0 TYPE1 TYPE0 0 0 0 0 10100000 brbbrrrr E612 1 EP2CFG Endpoint 2 Configuration VALID DIR TYPE1 TYPE0 SIZE 0 BUF1 BUF0 10100010 bbbbbrbb E613 1 EP4CFG Endpoint 4 Configuration VALID DIR TYPE1 TYPE0 0...

Page 17: ...slave FIFO Programmable Flag H DECIS PKTSTAT 0 OUT PFC10 OUT PFC9 0 0 PFC8 00001000 bbrbbrrb E637 H S 1 EP8FIFOPFL 10 Endpoint 8 slave FIFO Programmable Flag L PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0...

Page 18: ...CRC5 CRC4 CRC3 CRC2 CRC1 CRC0 10111010 RW E67F 1 UDMACRC QUALIFIER UDMA CRC Qualifier QENABLE 0 0 0 QSTATE QSIGNAL2 QSIGNAL1 QSIGNAL0 00000000 brrrbbbb USB CONTROL E680 1 USBCS USB Control Status HSM...

Page 19: ...Data Pointer high address byte A15 A14 A13 A12 A11 A10 A9 A8 xxxxxxxx RW E6B4 1 SUDPTRL Set up Data Pointer low address byte A7 A6 A5 A4 A3 A2 A1 0 xxxxxxx0 bbbbbbbr E6B5 1 SUDPTRCTL Set up Data Point...

Page 20: ...x x x x x x x xxxxxxxx W 3 Reserved E6F0 1 XGPIFSGLDATH GPIF Data H 16 bit mode only D15 D14 D13 D12 D11 D10 D9 D8 xxxxxxxx RW E6F1 1 XGPIFSGLDATLX Read Write GPIF Data L trigger transaction D7 D6 D5...

Page 21: ...upt 2 clear x x x x x x x x xxxxxxxx W A2 1 Reserved x x x x x x x x xxxxxxxx W A3 5 Reserved A8 1 IE Interrupt Enable bit addressable EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 00000000 RW A9 1 Reserved AA 1 EP2...

Page 22: ...d D8 1 EICON 12 External Interrupt Control SMOD1 1 ERESI RESI INT6 0 0 0 01000000 RW D9 7 Reserved E0 1 ACC Accumulator bit address able D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW E1 7 Reserved E8 1 EIE 12 E...

Page 23: ...e SCL and SDA pins which are 3 3V tolerant DC Voltage Applied to Outputs in High Z State 0 5V to VCC 0 5V Maximum Power Dissipation From AVcc Supply 90 mW From IO Supply 36 mW From Core Supply 95 mW S...

Page 24: ...Voltage HIGH IOUT 4 mA VCC_IO 0 4 V VOL Output LOW Voltage IOUT 4 mA 0 4 V IOH Output Current HIGH 4 mA IOL Output Current LOW 4 mA CIN Input Pin Capacitance Except D D 10 pF D D 15 pF ISUSP Suspend...

Page 25: ...Clock Set up Time 9 2 ns tDAH GPIF Data Hold Time 0 ns tXGD Clock to GPIF Data Output Propagation Delay 11 ns tXCTL Clock to CTLX Output Propagation Delay 6 7 ns Notes 17 Dashed lines denote signals w...

Page 26: ...E Turn on to FIFO Data Valid 10 5 ns tOEoff SLOE Turn off to FIFO Data Hold 2 15 10 5 ns tXFLG Clock to FLAGS Output Propagation Delay 9 5 ns tXFD Clock to FIFO Data Output Propagation Delay 11 ns Tab...

Page 27: ...ronous parameter values use internal IFCLK setting at 48 MHz Table 9 5 Slave FIFO Asynchronous Read Parameters 20 Parameter Description Min Max Unit tRDpwl SLRD Pulse Width LOW 50 ns tRDpwh SLRD Pulse...

Page 28: ...ck Set up Time 18 1 ns tWRH Clock to SLWR Hold Time 0 ns tSFD FIFO Data to Clock Set up Time 10 64 ns tFDH Clock to FIFO Data Hold Time 0 ns tXFLG Clock to FLAGS Output Propagation Time 9 5 ns Table 9...

Page 29: ...opagation Delay 70 ns FLAGS tXFLG IFCLK PKTEND tSPE tPEH Figure 9 6 Slave FIFO Synchronous Packet End Strobe Timing Diagram 17 Table 9 9 Slave FIFO Synchronous Packet End Strobe Parameters with Intern...

Page 30: ...e 9 7 shows this scenario X is the value the AUTOINLEN register is set to when the IN endpoint is configured to be in auto mode Figure 9 7 shows a scenario where two packets are being committed The fi...

Page 31: ...ff SLOE Deassert to FIFO DATA Hold 2 15 10 5 ns Table 9 13 Slave FIFO Address to Flags Data Parameters Parameter Description Min Max Unit tXFLG FIFOADR 1 0 to FLAGS Output Propagation Delay 10 7 ns tX...

Page 32: ...1 0 to Clock Set up Time 25 ns tFAH Clock to FIFOADR 1 0 Hold Time 10 ns Slave FIFO Asynchronous Address Parameters 20 Parameter Description Min Max Unit tSFA FIFOADR 1 0 to SLRD SLWR PKTEND Set up T...

Page 33: ...ead condition The FIFO pointer is updated on the rising edge of the IFCLK while SLRD is asserted This starts the propagation of data from the newly addressed location to the data bus After a propagati...

Page 34: ...ated on each rising edge of IFCLK In Figure 9 15 once the four bytes are written to the FIFO SLWR is deasserted The short 4 byte packet can be committed to the host by asserting the PKTEND signal Ther...

Page 35: ...ivating edge of SLRD In Figure 9 16 data N is the first valid data read from the FIFO For data toappearonthe databusduringthe read cycle forexample SLRD is asserted SLOE MUST be in an asserted state S...

Page 36: ...so updated after tXFLG from the deasserting edge of SLWR The same sequence of events is shown for a burst write and is indicated by the timing marks of T 0 through 5 Note In the burst write mode once...

Page 37: ...8051 Address Data Busses CY7C68053 56BAXI 56 VFBGA Lead Free 16K 24 Development Tool Kit CY3687 MoBL USB FX2LP18 Development Kit TOP VIEW PIN A1 CORNER 0 50 3 50 5 00 0 10 BOTTOM VIEW 0 10 4X 3 50 5 0...

Page 38: ...rd is required to maintain signal quality Specify impedance targets ask your board vendor what they can achieve To control impedance maintain trace widths and trace spac ing to within specifications M...

Page 39: ...10 B 465471 See ECN OSG Changed the recommendation for the pull up resistors on I2 C Split Icc into 4 different values corresponding to the different voltage supplies Changed Isus typical to 20uA and...

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