Cypress Semiconductor MoBL-USB CY7C68053, Specification Sheet, Page: 13 / 39

CY7C68053
Document # 001-06120 Rev *F Page 13 of 39
6F PA4 or
FIFOADR0
I/O/Z I
(PA4)
Multiplexed pin whose function is selected by:
IFCONFIG[1:0].
PA4 is a bidirectional IO port pin.
FIFOADR0 is an input-only address select for the slave FIFO’s connected
to FD[7:0] or FD[15:0].
8C PA5 or
FIFOADR1
I/O/Z I
(PA5)
Multiplexed pin whose function is selected by:
IFCONFIG[1:0].
PA5 is a bidirectional IO port pin.
FIFOADR1 is an input-only address select for the slave FIFO’s connected
to FD[7:0] or FD[15:0].
7C PA6 or
PKTEND
I/O/Z I
(PA6)
Multiplexed pin whose function is selected by the IFCONFIG[1:0] bits.
PA6 is a bidirectional IO port pin.
PKTEND is an input used to commit the FIFO packet data to the endpoint
and whose polarity is programmable using FIFOPINPOLAR.5.
6C PA7 or
FLAGD or
SLCS#
I/O/Z I
(PA7)
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
PORTACFG.7 bits.
PA7 is a bidirectional IO port pin.
FLAGD is a programmable slave FIFO output status flag signal.
SLCS# gates all other slave FIFO enable/strobes
Port B
3H PB0 or
FD[0]
I/O/Z I
(PB0)
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1:0].
PB0 is a bidirectional IO port pin.
FD[0] is the bidirectional FIFO/GPIF data bus.
4F PB1 or
FD[1]
I/O/Z I
(PB1)
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1:0].
PB1 is a bidirectional IO port pin.
FD[1] is the bidirectional FIFO/GPIF data bus.
4H PB2 or
FD[2]
I/O/Z I
(PB2)
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1:0].
PB2 is a bidirectional IO port pin.
FD[2] is the bidirectional FIFO/GPIF data bus.
4G PB3 or
FD[3]
I/O/Z I
(PB3)
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1:0].
PB3 is a bidirectional IO port pin.
FD[3] is the bidirectional FIFO/GPIF data bus.
5H PB4 or
FD[4]
I/O/Z I
(PB4)
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1:0].
PB4 is a bidirectional IO port pin.
FD[4] is the bidirectional FIFO/GPIF data bus.
5G PB5 or
FD[5]
I/O/Z I
(PB5)
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1:0].
PB5 is a bidirectional IO port pin.
FD[5] is the bidirectional FIFO/GPIF data bus.
5F PB6 or
FD[6]
I/O/Z I
(PB6)
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1:0].
PB6 is a bidirectional IO port pin.
FD[6] is the bidirectional FIFO/GPIF data bus.
6H PB7 or
FD[7]
I/O/Z I
(PB7)
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1:0].
PB7 is a bidirectional IO port pin.
FD[7] is the bidirectional FIFO/GPIF data bus.
Table 4-1. FX2LP18 Pin Descriptions (continued)
[9]
56 VFBGA Name Type Default Description
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