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MoBL

®

 CY62128E

Document #: 38-05485 Rev. *F

Page 7 of 12

Figure 4.  Write Cycle No. 2 

(CE1 or CE2 Controlled) 

[11, 15, 19, 20]

Figure 5.  Write Cycle No. 3 

(WE Controlled, OE LOW) 

[11, 20]

Truth Table

CE

1

CE

2

WE

OE

Inputs/Outputs

Mode

Power

H

X

X

X

High-Z

Deselect/Power down

Standby (I

SB

)

X

L

X

X

High-Z

Deselect/Power down

Standby (I

SB

)

L

H

H

L

Data Out

Read

Active (I

CC

)

L

H

L

X

Data In

Write

Active (I

CC

)

L

H

H

H

High-Z

Selected, Outputs Disabled

Active (I

CC

)

Switching Waveforms

 (continued)

t

WC

DATA VALID

t

AW

t

SA

t

PWE

t

HA

t

HD

t

SD

t

SCE

ADDRESS

CE

DATA IO

WE

DATA VALID

t

HD

t

SD

t

LZWE

t

PWE

t

SA

t

HA

t

AW

t

SCE

t

WC

t

HZWE

ADDRESS

CE

WE

DATA IO

NOTE 21

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Summary of Contents for MoBL CY62128E

Page 1: ...c power down feature that significantly reduces power consumption when addresses are not toggling Placing the device into standby mode reduces power consumption by more than 99 percent when deselected CE1 HIGH or CE2 LOW The eight input and output pins IO0 through IO7 are placed in a high impedance state when the device is deselected CE1 HIGH or CE2 LOW the outputs are disabled OE HIGH or a write ...

Page 2: ...7 A16 A14 A12 WE VCC A4 A13 A8 A9 OE TSOP I Top View not to scale 1 6 2 3 4 5 7 32 27 31 30 29 28 26 21 25 24 23 22 19 20 IO2 IO1 GND IO7 IO4 IO5 IO6 IO0 CE1 A11 A5 17 18 8 9 10 11 12 13 14 15 16 CE2 A15 NC A10 IO3 A1 A0 A3 A2 1 2 3 4 5 6 7 8 9 10 11 14 31 32 12 13 16 15 29 30 21 22 19 20 27 28 25 26 17 18 23 24 32 Pin SOIC Top View NC A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 IO0 ...

Page 3: ...L 2 1 mA 0 4 0 4 V VIH Input HIGH Voltage VCC 4 5V to 5 5V 2 2 VCC 0 5 2 2 VCC 0 5 V VIL Input LOW voltage VCC 4 5V to 5 5V 0 5 0 8 0 5 0 8 V IIX Input Leakage Current GND VI VCC 1 1 4 4 μA IOZ Output Leakage Current GND VO VCC Output Disabled 1 1 4 4 μA ICC VCC Operating Supply Current f fmax 1 tRC VCC VCC max IOUT 0 mA CMOS levels 11 16 11 35 mA f 1 MHz 1 3 2 1 3 4 ISB2 8 Automatic CE Power down...

Page 4: ...r Description Conditions Min Typ 3 Max Unit VDR VCC for Data Retention 2 V ICCDR 8 Data Retention Current VCC VDR CE1 VCC 0 2V or CE2 0 2V VIN VCC 0 2V or VIN 0 2V Ind l Auto A 4 μA Auto E 30 μA tCDR 9 Chip Deselect to Data Retention Time 0 ns tR 10 Operation Recovery Time tRC ns Data Retention Waveform 11 VCC min VCC min tCDR VDR 2 0V DATA RETENTION MODE tR VCC CE Notes 10 Full device AC operatio...

Page 5: ...ddress Setup to Write Start 0 0 ns tPWE WE Pulse Width 35 40 ns tSD Data Setup to Write End 25 25 ns tHD Data Hold from Write End 0 0 ns tHZWE WE LOW to High Z 13 14 18 20 ns tLZWE WE HIGH to Low Z 13 10 10 ns Notes 12 Test conditions for all parameters other than tri state parameters assume signal transition time of 3ns 1V ns or less timing reference levels of 1 5V input pulse levels of 0 to 3V a...

Page 6: ...tPD IMPEDANCE ICC ISB HIGH ADDRESS CE DATA OUT VCC SUPPLY CURRENT OE DATA VALID tHD tSD tPWE tSA tHA tAW tSCE tWC tHZOE ADDRESS CE WE DATA IO OE NOTE 21 Notes 16 The device is continuously selected OE CE1 VIL CE2 VIH 17 WE is HIGH for read cycle 18 Address valid before or similar to CE1 transition LOW and CE2 transition HIGH 19 Data IO is high impedance if OE VIH 20 If CE1 goes HIGH or CE2 goes LO...

Page 7: ... Power H X X X High Z Deselect Power down Standby ISB X L X X High Z Deselect Power down Standby ISB L H H L Data Out Read Active ICC L H L X Data In Write Active ICC L H H H High Z Selected Outputs Disabled Active ICC Switching Waveforms continued tWC DATA VALID tAW tSA tPWE tHA tHD tSD tSCE ADDRESS CE DATA IO WE DATA VALID tHD tSD tLZWE tPWE tSA tHA tAW tSCE tWC tHZWE ADDRESS CE WE DATA IO NOTE ...

Page 8: ...C Pb free Industrial CY62128ELL 45ZAXI 51 85094 32 pin STSOP Pb free CY62128ELL 45ZXI 51 85056 32 pin TSOP Type I Pb free 45 CY62128ELL 45SXA 51 85081 32 pin 450 Mil SOIC Pb free Automotive A CY62128ELL 45ZXA 51 85056 32 pin TSOP Type I Pb free 55 CY62128ELL 55SXE 51 85081 32 pin 450 Mil SOIC Pb free Automotive E CY62128ELL 55ZAXE 51 85094 32 pin STSOP Pb free Contact your local Cypress sales repr...

Page 9: ...MoBL CY62128E Document 38 05485 Rev F Page 9 of 12 Figure 7 32 pin Shrunk Thin Small Outline Package 8 x 13 4 mm 51 85094 51 85094 D Feedback ...

Page 10: ...MoBL CY62128E Document 38 05485 Rev F Page 10 of 12 Figure 8 32 pin Thin Small Outline Package Type I 8 x 20 mm 51 85056 Feedback ...

Page 11: ... 11 Changed max of ISB1 ISB2 and ICCDR from 1 0 μA to 1 5 μA B 461631 See ECN NXR Converted from Preliminary to Final Included Automotive Range and 55 ns speed bin Removed 35 ns speed bin Removed L version of CY62128E Removed Reverse TSOP I package from Product offering Changed ICC Typ from 8 mA to 11 mA and ICC max from 12 mA to 16 mA for f fmax Changed ICC max from 1 5 mA to 2 0 mA for f 1 MHz R...

Page 12: ...r the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS...

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