Cypress Semiconductor ISR 37000 CPLD Specification Sheet Download

Page: 5 / 64

Ultra37000 CPLD Family

Document #: 38-03007 Rev. *E

Page 5 of 64

The buried macrocell also supports input register capability.

The buried macrocell can be configured to act as an input

associated with the neighboring macrocell. The output of all

buried macrocells is sent directly to the PIM regardless of its

configuration.

I/O Macrocell
Figure 2

illustrates the architecture of the I/O macrocell. The

I/O macrocell supports the same functions as the buried

macrocell with the addition of I/O capability. At the output of the

macrocell, a polarity control mux is available to select active

LOW or active HIGH signals. This has the added advantage

of allowing significant logic reduction to occur in many appli-

cations.
The Ultra37000 macrocell features a feedback path to the PIM

separate from the I/O pin input path. This means that if the

macrocell is buried (fed back internally only), the associated

I/O pin can still be used as an input.

Bus Hold Capabilities on all I/Os

Bus-hold, which is an improved version of the popular internal

pull-up resistor, is a weak latch connected to the pin that does

not degrade the device’s performance. As a latch, bus-hold

maintains the last state of a pin when the pin is placed in a

high-impedance state, thus reducing system noise in

bus-interface applications. Bus-hold additionally allows

unused device pins to remain unconnected on the board,

which is particularly useful during prototyping as designers can

route new signals to the device without cutting trace connec-

tions to V

or GND. For more information, see the application

note

Understanding Bus-Hold—A Feature of Cypress CPLDs

Programmable Slew Rate Control

Each output has a programmable configuration bit, which sets

the output slew rate to fast or slow. For designs concerned with

meeting FCC emissions standards the slow edge provides for

lower system noise. For designs requiring very high perfor-

mance the fast edge rate provides maximum system perfor-

mance.

C2 C3

DECODE

C2 C3

DECODE

0
1
2

C6 C5

“0”
“1”

D/T/L Q

FEEDBACK TO PIM

BLOCK RESET

−

TERMS

I/O MACROCELL

I/O CELL

FROM PTM

D/T/L Q

FROM PTM

FEEDBACK TO PIM

BURIED MACROCELL

ASYNCHRONOUS

PRODUCT

−

TERMS

PRODUCT

C24

C0 C1 C24

C25

4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3)
1 ASYNCHRONOUS CLOCK(PTCLK)

BLOCK PRESET

ASYNCHRONOUS

FAST

SLOW

C26

SLEW

OE0 OE1

Figure 2. I/O and Buried Macrocells

[+] Feedback

Summary of Contents for ISR 37000 CPLD

Page 1: ... Each logic block features its own product term array product term allocator and 16 macrocells The PIM distributes signals from the logic block outputs and all input pins to the logic block inputs All of the Ultra37000 devices are electrically erasable and In System Reprogrammable ISR which simplifies both design and manufacturing flows thereby reducing costs The ISR feature provides the ability t...

Page 2: ... X X CY37384 X X CY37512 X X X Device Package Offering and I O Count Device 44 Lead TQFP 44 Lead PLCC 44 Lead CLCC 84 Lead PLCC 84 Lead CLCC 100 Lead TQFP 160 Lead TQFP 160 Lead CQFP 208 Lead PQFP 208 Lead CQFP 292 Lead PBGA 388 Lead PBGA CY37032 37 37 CY37064 37 37 37 69 69 CY37128 69 69 69 133 CY37192 125 CY37256 133 133 165 197 CY37384 165 197 CY37512 165 165 197 269 3 3V Selection Guide Genera...

Page 3: ...uct term array an intelligent product term allocator 16 macrocells and a number of I O cells The number of I O cells varies depending on the device used Refer to Figure 1 for the block diagram Product Term Array Each logic block features a 72 x 87 programmable product term array This array accepts 36 inputs from the PIM which originate from macrocell feedbacks and device pins Active LOW and active...

Page 4: ...on The software automatically takes advantage of this capability the user does not have to intervene Note that neither product term sharing nor product term steering have any effect on the speed of the product All worst case steering and sharing configurations have been incorporated in the timing specifications for the Ultra37000 devices Ultra37000 Macrocell Within each logic block there are 16 ma...

Page 5: ...egrade the device s performance As a latch bus hold maintains the last state of a pin when the pin is placed in a high impedance state thus reducing system noise in bus interface applications Bus hold additionally allows unused device pins to remain unconnected on the board which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connec...

Page 6: ...also supports user configurable polarity selection Timing Model One of the most important features of the Ultra37000 family is the simplicity of its timing All delays are worst case and system performance is unaffected by the features used Figure 5 illustrates the true timing model for the 167 MHz devices in high speed mode For combinatorial paths any input to any output incurs a 6 5 ns worst case...

Page 7: ... It allows comparison of waveforms before and after design changes Warp Enterprise Warp Enterprise provides even more features It provides unlimited timing simulation and source level behavioral simulation as well as a debugger It has the ability to generate graphical HDL blocks from HDL text It can even generate testbenches Warp is available for PC and UNIX platforms Some features are not availab...

Page 8: ...37000 devices to complete the desired reconfiguring or diagnostic operations Contact your local sales office for information on availability of this option The fourth method for programming Ultra37000 devices is to use the same programmer that is currently being used to program FLASH370i devices For all pinout electrical and timing requirements refer to device data sheets For ISR cable and softwar...

Page 9: ... 16 I Os 16 I Os I O0 I O15 I O16 I O31 4 4 4 16 16 TDI TCK TMS TDO JTAG Tap Controller 1 PIM JTAGEN LOGIC BLOCK D LOGIC BLOCK C LOGIC BLOCK A LOGIC BLOCK B 36 16 36 16 36 16 36 16 Input Clock Input 16 I Os 16 I Os 16 I Os 16 I Os I O0 I O15 I O16 I O31 I O48 I O63 I O32 I O47 4 4 4 32 32 TDI TCK TMS TDO JTAG Tap Controller 1 PIM CY37064 CY37064V Feedback ...

Page 10: ...I O80 I O95 I O64 I O79 16 I Os 16 I Os 16 I Os 16 I Os 16 I Os 16 I Os 16 I Os JTAGEN LOGIC BLOCK H LOGIC BLOCK L LOGIC BLOCK I LOGIC BLOCK J LOGIC BLOCK K LOGIC BLOCK A LOGIC BLOCK B LOGIC BLOCK C LOGIC BLOCK D LOGIC BLOCK E LOGIC BLOCK G LOGIC BLOCK F 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 PIM Input Clock Input 10 I Os 10 I Os 10 I Os 10 I Os 10 I Os 10 I Os 10 ...

Page 11: ...GIC BLOCK F 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 PIM Input Clock Input 12 I Os 12 I Os 12 I Os 12 I Os 12 I Os 12 I Os 12 I Os 12 I Os 12 I Os 12 I Os 12 I Os 12 I Os 12 I Os 12 I Os 12 I Os 12 I Os I O0 I O11 I O12 I O23 I O24 I O35 I O36 I O47 I O48 I O59 I O60 I O71 I O72 I O83 I O84 I O95 I O180 I O191 I O168 I O179 I O156 I O167 I O14...

Page 12: ...16 36 16 36 16 36 16 36 16 36 16 PIM Input Clock Input 12 I Os 12 I Os 12 I Os 12 I Os 12 I Os 12 I Os 12 I Os 12 I Os 12 I Os 12 I Os 12 I Os I O0 I O11 I O12 I O23 I O24 I O35 I O48 I O59 I O60 I O71 I O72 I O83 I O168 I O191 I O156 I O179 I O144 I O167 I O120 I O143 I O108 I O131 4 4 4 96 96 TDI TCK TMS TDO JTAG Tap Controller 1 LOGIC BLOCK AJ LOGIC BLOCK BC 16 16 12 I Os I O96 I O119 LOGIC BLO...

Page 13: ...0 I O11 I O12 I O23 I O24 I O35 I O36 I O47 I O48 I O59 I O60 I O71 I O72 I O83 I O84 I O95 I O252 I O263 I O240 I O251 I O228 I O239 I O216 I O227 I O204 I O215 4 4 4 TDI TCK TMS TDO JTAG Tap Controller 1 PIM 16 36 36 16 LOGIC BLOCK AI LOGIC BLOCK BH 12 I Os I O96 I O107 16 36 36 16 LOGIC BLOCK AJ LOGIC BLOCK BG 12 I Os 12 I Os I O108 I O119 I O192 I O203 16 36 36 16 LOGIC BLOCK AK LOGIC BLOCK BF...

Page 14: ...s 7 2 0 VCCmax V VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs 7 0 5 0 8 V IIX Input Load Current VI GND OR VCC Bus Hold Disabled 10 10 µA IOZ Output Leakage Current VO GND or VCC Output Disabled Bus Hold Disabled 50 50 µA IOS OutputShortCircuitCurrent 5 8 VCC Max VOUT 0 5V 30 160 mA IBHL Input Bus Hold LOW Sustaining Current VCC Min VIL 0 8V 75 µA IBHH Input Bus Hold H...

Page 15: ... Cycles Normal Programming Conditions 2 1 000 10 000 Cycles Operating Range 2 Range Ambient Temperature 2 Junction Temperature VCC 10 Commercial 0 C to 70 C 0 C to 90 C 3 3V 0 3V Industrial 40 C to 85 C 40 C to 105 C 3 3V 0 3V Military 3 55 C to 125 C 55 C to 130 C 3 3V 0 3V 3 3V Device Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min Max Unit VOH Outpu...

Page 16: ...ons Min Typ Unit N Minimum Reprogramming Cycles Normal Programming Conditions 2 1 000 10 000 Cycles AC Characteristics 5 0V AC Test Loads and Waveforms 3 3V AC Test Loads and Waveforms 90 10 3 0V GND 90 10 ALL INPUT PULSES 5V OUTPUT 35 pF INCLUDING JIG AND SCOPE 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE a b 2 ns OUTPUT 238Ω COM L 319Ω MIL 170Ω COM L 236Ω MIL 99Ω COM L 136Ω MIL Equivalent to THÉVENIN ...

Page 17: ...ent Output Latch ns Synchronous Clocking Parameters tCO 14 15 Synchronous Clock CLK0 CLK1 CLK2 or CLK3 or Latch Enable to Output ns tS 13 Set Up Time from Input to Sync Clk CLK0 CLK1 CLK2 or CLK3 or Latch Enable ns tH Register or Latch Data Hold Time ns tCO2 13 14 15 Output Synchronous Clock CLK0 CLK1 CLK2 or CLK3 or Latch Enable to Combinatorial Output Delay Through Logic Array ns tSCS 13 Output ...

Page 18: ...S 1 tS tH or 1 tCO 5 MHz fMAX2 Maximum Frequency Data Path in Output Registered Latched Mode Lesser of 1 tWL tWH 1 tS tH or 1 tCO 5 MHz fMAX3 Maximum Frequency with External Feedback Lesser of 1 tCO tS or 1 tWL tWH 5 MHz fMAX4 Maximum Frequency in Pipelined Mode Lesser of 1 tCO tIS 1 tICS 1 tWL tWH 1 tIS tIH or 1 tSCS 5 MHz Reset Preset Parameters tRW Asynchronous Reset Width 5 ns tRR 13 Asynchron...

Page 19: ...SCS 13 5 6 6 5 7 8 16 10 12 15 ns tSL 13 7 5 7 5 8 5 9 10 12 15 15 ns tHL 0 0 0 0 0 0 0 0 ns Product Term Clocking Parameters tCOPT 13 14 15 7 10 10 13 13 13 15 20 ns tSPT 2 5 2 5 2 5 3 5 5 5 6 7 ns tHPT 2 5 2 5 2 5 3 5 5 5 6 7 ns tISPT 13 0 0 0 0 0 0 0 0 ns tIHPT 6 6 5 6 5 7 5 9 11 14 19 ns tCO2PT 13 14 15 12 14 15 19 19 21 24 30 ns Pipelined Mode Parameters tICS 13 5 6 6 7 8 16 10 12 15 ns Opera...

Page 20: ... ns tH JTAG 20 20 20 20 20 20 20 20 ns tCO JTAG 20 20 20 20 20 20 20 20 ns fJTAG 20 20 20 20 20 20 20 20 MHz Switching Characteristics Over the Operating Range continued 12 Parameter 200 MHz 167 MHz 154 MHz 143 MHz 125 MHz 100 MHz 83 MHz 66 MHz Unit Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Switching Waveforms Combinatorial Output Registered Output with Synchronous Clocking N...

Page 21: ...h the Array Registered Output with Product Term Clocking Input Coming From Adjacent Buried Register Latched Output Switching Waveforms continued tSPT INPUT PRODUCT TERM tCOPT REGISTERED OUTPUT tHPT CLOCK tISPT INPUT PRODUCT TERM tCO2PT REGISTERED OUTPUT tIHPT CLOCK tSL INPUT LATCH ENABLE tCO LATCHED OUTPUT tHL tPDL Feedback ...

Page 22: ...o Clock Latched Input Switching Waveforms continued tIS REGISTERED INPUT INPUT REGISTER CLOCK tICO COMBINATORIAL OUTPUT tIH CLOCK tWL tWH INPUT REGISTER CLOCK OUTPUT REGISTER CLOCK tSCS tICS tIS LATCHED INPUT LATCH ENABLE tICO COMBINATORIAL OUTPUT tIH tPDL tWL tWH LATCH ENABLE Feedback ...

Page 23: ...et Asynchronous Preset Output Enable Disable Switching Waveforms continued tICS LATCHED INPUT OUTPUT LATCH ENABLE LATCHED OUTPUT tPDLL LATCH ENABLE tWL tWH tICOL INPUT LATCH ENABLE tSL tHL INPUT tRO REGISTERED OUTPUT CLOCK tRR tRW INPUT tPO REGISTERED OUTPUT CLOCK tPR tPW INPUT tER OUTPUTS tEA Feedback ...

Page 24: ...ency M H z Icc mA H igh Speed Low Power The typical pattern is a 16 bit up counter per logic block with outputs disabled VCC 5 0V TA Room Temperature The typical pattern is a 16 bit up counter per logic block with outputs disabled VCC 5 0V TA Room Temperature 0 10 20 30 40 50 60 70 80 90 0 20 40 60 80 100 120 140 160 180 Frequency M Hz Icc mA Low Power High Speed Feedback ...

Page 25: ...0 Frequency M H z Icc mA Low P ow er H igh S peed The typical pattern is a 16 bit up counter per logic block with outputs disabled VCC 5 0V TA Room Temperature 0 50 100 150 200 250 300 0 20 40 60 80 100 120 140 160 180 Frequency M H z Icc mA Low Power H igh Speed The typical pattern is a 16 bit up counter per logic block with outputs disabled VCC 5 0V TA Room Temperature Feedback ...

Page 26: ...ncy M H z Icc mA Low P ow er H igh S peed The typical pattern is a 16 bit up counter per logic block with outputs disabled VCC 5 0V TA Room Temperature 0 50 100 150 200 250 300 350 400 450 500 0 20 40 60 80 100 120 140 160 Frequency M Hz Icc mA Low Power High Speed The typical pattern is a 16 bit up counter per logic block with outputs disabled VCC 5 0V TA Room Temperature Feedback ...

Page 27: ...mA Low P ow er H igh S peed The typical pattern is a 16 bit up counter per logic block with outputs disabled VCC 5 0V TA Room Temperature Typical 3 3V Power Consumption CY37032V 0 5 10 15 20 25 30 0 20 40 60 80 100 120 140 160 Frequency MHz Icc mA Low Power High Speed The typical pattern is a 16 bit up counter per logic block with outputs disabled VCC 3 3V TA Room Temperature Feedback ...

Page 28: ... Icc mA Low Power High Speed The typical pattern is a 16 bit up counter per logic block with outputs disabled VCC 3 3V TA Room Temperature 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 F re q u e n c y M H z Icc mA L o w P o w e r H igh S p e e d The typical pattern is a 16 bit up counter per logic block with outputs disabled VCC 3 3V TA Room Temperature Feedback ...

Page 29: ...H z Icc mA L o w P o w e r H ig h S p e e d The typical pattern is a 16 bit up counter per logic block with outputs disabled VCC 3 3V TA Room Temperature 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 F re q u e n c y M H z Icc mA L o w P o w e r H ig h S p e e d The typical pattern is a 16 bit up counter per logic block with outputs disabled VCC 3 3V TA Room Temperature Feedbac...

Page 30: ...q u e n c y M H z Icc mA L o w P o w e r H ig h S p e e d The typical pattern is a 16 bit up counter per logic block with outputs disabled VCC 3 3V TA Room Temperature 0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 F r e q u e n c y M H z Icc mA L o w P o w e r H ig h S p e e d The typical pattern is a 16 bit up counter per logic block with outputs disabled VCC 3 3V TA Room Te...

Page 31: ...5 6 1 18 19 20 22 21 13 14 15 17 16 12 31 30 29 32 33 26 25 24 27 28 23 44 43 42 40 41 39 38 37 35 36 34 I O 13 TMS I O 19 TDO JTAGEN 44 pin PLCC J67 CLCC Y67 Top View I O27 TDI I O26 I O25 I O24 CLK1 I4 GND I3 CLK3 I2 I O23 I O22 I O21 I O5 TCK I O6 I O7 CLK2 I0 JTAGEN GND CLK0 I1 I O8 I O9 I O10 I O11 GND I O 20 I O 2 GND V CCO V CC I O 3 I O 4 I O 1 I O 0 I O 29 I O 30 I O 31 I O 28 I O 19 I O ...

Page 32: ...op View 84 lead PLCC J83 CLCC Y84 9 8 6 7 5 13 14 12 11 49 48 58 59 60 23 24 26 25 27 15 16 47 46 4 3 28 33 20 21 19 18 17 22 34 37 36 38 42 41 43 40 66 65 63 64 62 61 67 68 69 74 72 73 71 70 84 81 82 80 79 GND I O GND I O I O I O I O I O I O I O GND I O 55 I O 54 TDI I O 53 I O 52 I O 51 GND I O 49 CLK3 I 4 VCCO CLK2 I 3 I O 45 I O 44 GND I O I O 8 I O 9 I O 10 TCK I O11 I O12 I O13 CLK0 I 0 VCCO...

Page 33: ...GND I O 8 I O 9 I O10 I O11 I O15 VCCO GND CLK1 I1 I O16 I O17 CLK0 I0 90 91 I O 51 VCCO CLK 2 I 3 I O14 N C I O12 I O13 I O 45 I O 44 I O 43 I O 42 I O 41 I O 40 GND NC GND NC I O18 I O19 I O20 I O21 I O22 I O23 VCCO NC 18 19 20 21 22 23 24 25 83 82 81 80 79 78 77 76 58 57 56 55 54 53 52 51 43 44 45 46 48 49 50 GND I O 24 I O 25 I O 26 I O 27 I O 28 I O 29 I O 30 I O 31 V CCO V CC I O 32 I O 33 I...

Page 34: ... I O23 TMS VCC I O20 NC I O32 I O42 VCC TDO I O41 J NC I O26 I O28 NC I O31 I O33 I O35 I O37 I O39 I O40 K I O24 I O25 I O27 I O29 I O30 I O34 I O36 I O38 NC NC 1 2 3 4 5 6 7 8 9 10 A NC I O9 I O8 I O6 I O3 I O76 I O74 I O72 I O71 I O70 B I O11 I O10 I O7 I O5 I O2 I O77 VCC I O73 I O68 I O69 C I O12 I O13 TCK VCC I O4 I O1 I O78 I O75 VCC I O67 TDI I O66 D I O14 NC I O15 I O16 I O0 I O79 I O63 I...

Page 35: ... GND CLK1 I1 GND GND GND GND GND VCCO I O 48 I O 49 I O 50 I O 51 I O 53 I O 54 I O 55 I O 56 I O 57 I O 58 I O 59 I O 60 I O 61 I O 62 I O 63 I 2 V CCO V CC I O 64 I O 65 I O 66 I O 67 I O 68 I O 69 I O 70 I O 71 I O 72 I O 73 I O 74 I O 75 I O 78 I O 79 V CCO GND I O80 I O81 I O82 I O83 I O84 I O85 I O86 I O87 GND I O88 I O89 I O90 I O91 I O92 I O93 I O94 I O95 I O96 I O97 I O98 I O99 I O100 I O...

Page 36: ...I O43 I O44 I O45 GND CLK0 I0 VCCO GND CLK1 I1 GND GND GND GND GND VCCO NC I O 46 I O 47 I O 48 I O 49 I O 50 I O 51 I O 52 I O 53 I O 54 I O 55 I O 56 I O 57 I O 58 I O 59 I 2 V CCO V CC I O 60 I O 61 I O 62 I O 63 I O 64 I O 65 I O 66 I O 67 I O 68 I O 69 I O 70 I O 71 I O 73 I O 74 V CCO GND NC I O75 I O76 I O77 I O78 I O79 I O80 I O81 GND I O82 I O83 I O84 I O85 I O86 I O87 I O88 I O89 I O90 I...

Page 37: ...26 I O125 I O124 I O123 I O122 I O121 I O120 CLK3 I4 VCC GND VCCO GND CLK2 I3 I O119 I O118 I O117 I O116 I O115 NC I O114 I O113 I O112 I O111 I O110 VCCO GND I O109 I O108 I O107 I O106 I O105 I O104 I O103 I O102 I O101 I O100 GND I O 61 I O 62 I O 63 I O 64 TMS I O 65 I O 66 I O 67 I O 68 I O 69 GND I O 70 I O 71 I O 72 I O 73 I O 74 NC I O 75 I O 76 I O 77 I O 78 I O 79 I 2 V CC0 GND V CC I O...

Page 38: ...O37 I O36 GND GND GND GND GND GND I O148 I O147 I O146 I O145 J K I O42 I O40 I O41 VCC GND GND GND GND GND GND I O144 CLK3 I4 NC NC K L I O43 I O44 I O45 I O46 GND GND GND GND GND GND VCC CLK2 I3 I O143 NC L M I O47 CLK0 I0 CLK1 I1 I O48 GND GND GND GND GND GND I O139 I O140 I O141 I O142 M N I O49 I O50 I O51 GND GND GND GND GND GND GND GND I O136 I O137 I O138 N P I O52 I O53 I O55 I O58 I O131...

Page 39: ... I O41 I O40 VCC I O39 I O5 I O0 I O187 I O148 I O149 CLK3 I4 I O150 I O151 I O152 I O153 H GND GND I O47 I O46 CLK0 I0 I O45 I O44 GND GND I O144 I O145 CLK2 I3 I O146 I O147 GND GND J GND GND I O51 I O50 NC I O49 I O48 GND GND I O140 I O141 I2 I O142 I O143 GND GND K I O57 I O56 I O55 I O54 CLK1 I1 I O53 I O52 I O91 I O96 I O101 I O135 VCC I O136 I O137 I O138 I O139 L VCC I O60 I O59 I O58 TMS ...

Page 40: ...GND GND I O204 I4 I O197 M I O61 I O60 I1 GND GND GND GND GND GND GND GND I3 I O203 I O202 N I O64 VCC I O62 VCCO GND GND GND GND GND GND VCCO I O201 I O200 I O199 P I O65 I O66 I O67 VCCO GND GND GND GND GND GND VCCO I O196 VCC I O198 R I O68 I O69 I O70 GND GND GND GND GND GND GND GND I O193 I O194 I O195 T I O71 I O84 I O85 GND GND GND GND GND GND GND GND I O178 I O179 I O192 U I O88 I O87 I O8...

Page 41: ... I O205 I O206 I O207 I O208 I O209 K GND GND GND GND I O65 I O64 CLK0 I0 I O63 I O61 GND GND I O198 I O199 CLK2 I3 I O200 I O201 GND GND GND GND L GND GND GND GND I O69 I O68 NC I O67 I O66 GND GND I O193 I O195 I2 I O196 I O197 GND GND GND GND M I O89 I O88 I O87 I O86 I O85 I O84 CLK1 I1 I O71 I O70 I O126 I O132 I O192 I O194 VCC I O174 I O175 I O176 I O177 I O178 I O179 N VCC VCC VCC I O91 I ...

Page 42: ... Quad Flat Pack Commercial CY37064P44 200AXC A44 44 Lead Lead Free Thin Quad Flat Pack CY37064P44 200JC J67 44 Lead Plastic Leaded Chip Carrier CY37064P44 200JXC J67 44 Lead Lead Free Plastic Leaded Chip Carrier CY37064P84 200JC J83 84 Lead Plastic Leaded Chip Carrier CY37064P100 200AC A100 100 Lead Thin Quad Flat Pack CY37064P100 200AXC A100 100 Lead Lead Free Thin Quad Flat Pack C Y 3 7 5 1 2 V ...

Page 43: ...A44 44 Lead Thin Quad Flat Pack Commercial CY37064P44 125AXC A44 44 Lead Lead Free Thin Quad Flat Pack CY37064P44 125JC J67 44 Lead Plastic Leaded Chip Carrier CY37064P44 125JXC J67 44 Lead Lead Free Plastic Leaded Chip Carrier CY37064P84 125JC J83 84 Lead Plastic Leaded Chip Carrier CY37064P100 125AC A100 100 Lead Thin Quad Flat Pack CY37064P100 125AXC A100 100 Lead Lead Free Thin Quad Flat Pack ...

Page 44: ...ry 100 CY37128P84 100JC J83 84 Lead Plastic Leaded Chip Carrier Commercial CY37128P84 100JXC J83 84 Lead Lead Free Plastic Leaded Chip Carrier CY37128P100 100AC A100 100 Lead Thin Quad Flat Pack CY37128P100 100AXC A100 100 Lead Lead Free Thin Quad Flat Pack CY37128P160 100AC A160 160 Lead Thin Quad Flat Pack CY37128P160 100AXC A160 160 Lead Lead Free Thin Quad Flat Pack CY37128P84 100JI J83 84 Lea...

Page 45: ...Military 83 CY37256P160 83AC A160 160 Lead Thin Quad Flat Pack Commercial CY37256P160 83AXC A160 160 Lead Lead Free Thin Quad Flat Pack CY37256P208 83NC N208 208 Lead Plastic Quad Flat Pack CY37256P256 83BGC BG292 292 Ball Plastic Ball Grid Array CY37256P160 83AI A160 160 Lead Thin Quad Flat Pack Industrial CY37256P160 83AXI A160 160 Lead Lead Free Thin Quad Flat Pack CY37256P208 83NI N208 208 Lea...

Page 46: ...ad Flat Pack Industrial CY37512P256 83BGI BG292 292 Ball Plastic Ball Grid Array CY37512P352 83BGI BG388 388 Ball Plastic Ball Grid Array 5962 9952501QZC U208 208 Lead Ceramic Quad Flat Pack Military 5 0V Ordering Information continued Macrocells Speed MHz Ordering Code Package Name Package Type Operating Range 3 3V Ordering Information Macrocells Speed MHz Ordering Code Package Name Package Type ...

Page 47: ...VP100 125AXC A100 100 Lead Lead Free Thin Quad Flat Pack CY37128VP100 125BBC BB100 100 Ball Fine Pitch Ball Grid Array CY37128VP160 125AC A160 160 Lead Thin Quad Flat Pack CY37128VP160 125AXC A160 160 Lead Lead Free Thin Quad Flat Pack CY37128VP160 125AI A160 160 Lead Thin Quad Flat Pack Industrial CY37128VP160 125AXI A160 160 Lead Lead Free Thin Quad Flat Pack 83 CY37128VP100 83AC A100 100 Lead T...

Page 48: ...08 208 Lead Plastic Quad Flat Pack Commercial CY37384VP256 83BGC BG292 292 Ball Plastic Ball Grid Array 66 CY37384VP208 66NC N208 208 Lead Plastic Quad Flat Pack Commercial CY37384VP256 66BGC BG292 292 Ball Plastic Ball Grid Array CY37384VP208 66NI N208 208 Lead Plastic Quad Flat Pack Industrial CY37384VP256 66BGI BG292 292 Ball Plastic Ball Grid Array 512 83 CY37512VP208 83NC N208 208 Lead Plasti...

Page 49: ...7000 CPLD Family Document 38 03007 Rev E Page 49 of 64 Package Diagrams 51 85064 B 44 Lead Lead Pb Free Thin Plastic Quad Flat Pack A44 51 85003 A 44 Lead Lead Pb Free Plastic Leaded Chip Carrier J67 Feedback ...

Page 50: ...Ultra37000 CPLD Family Document 38 03007 Rev E Page 50 of 64 Package Diagrams continued 44 Lead Ceramic Leaded Chip Carrier Y67 51 80014 Feedback ...

Page 51: ...D Family Document 38 03007 Rev E Page 51 of 64 Package Diagrams continued 48 Ball 7 0 mm x 7 0 mm x 1 2 mm 0 80 pitch Thin BGA BA48D 51 85109 C 51 85006 A 84 Lead Lead Pb Free Plastic Leaded Chip Carrier J83 Feedback ...

Page 52: ...Ultra37000 CPLD Family Document 38 03007 Rev E Page 52 of 64 Package Diagrams continued 84 Lead Ceramic Leaded Chip Carrier Y84 51 80095 A Feedback ...

Page 53: ...Ultra37000 CPLD Family Document 38 03007 Rev E Page 53 of 64 Package Diagrams continued 51 85048 B 100 Lead Lead Pb Free Thin Plastic Quad Flat Pack TQFP A100 Feedback ...

Page 54: ...Ultra37000 CPLD Family Document 38 03007 Rev E Page 54 of 64 Package Diagrams continued 100 Ball Thin Ball Grid Array 11 x 11 x 1 4 mm BB100 51 85107 B Feedback ...

Page 55: ...Ultra37000 CPLD Family Document 38 03007 Rev E Page 55 of 64 Package Diagrams continued 51 85049 B 160 Lead Lead Pb Free Thin Plastic Quad Flat Pack 24 x 24 x 1 4 mm TQFP A160 Feedback ...

Page 56: ...03 080 0 500 020 0 050 002 020 008 0 51 0 20 006 001 0 15 0 02 TYP 0 300 012 TYP 0 650 0256 1 228 010 31 20 0 25 1 102 004 28 00 0 10 SQ SQ PIN 1 25 35 0 10 998 004 TYP SEE DETAIL A 008 MIN 0 7 0 20 MIN DETAIL A REFERENCE JEDEC N A PKG WEIGHT 6 7gms 0 MIN R 0 13 005 MIN 160 Lead Ceramic Quad Flatpack Cavity Up U162 51 80106 A Feedback ...

Page 57: ...Ultra37000 CPLD Family Document 38 03007 Rev E Page 57 of 64 Package Diagrams continued 208 Lead Plastic Quad Flatpack N208 51 85069 B Feedback ...

Page 58: ...H 0 500 020 0 050 002 3 94 155 3 43 135 006 001 0 15 0 02 020 008 0 51 0 20 1 229 010 31 22 0 25 1 102 008 28 00 0 10 TYP 0 50 0197 TYP 0 20 008 SQ SQ PIN 1 SEE DETAIL A 008 MIN 0 7 0 20 MIN DETAIL A REFERENCE JEDEC N A PKG WEIGHT 6 7gms 0 MIN R 0 13 005 MIN 51 80105 B 208 Lead Ceramic Quad Flatpack Cavity Up U208 Feedback ...

Page 59: ...M C Ø0 45 0 05 256X CPLD DEVICES 37K 39K 0 25 C 0 70 0 05 C SEATING PLANE 0 15 C 16 15 14 13 12 11 T R P M N L N T R P M L K J F G H E D A C B 16 15 13 14 12 10 11 9 2 8 7 6 5 4 3 1 A B Ø0 50 256X ALL OTHER DEVICES 0 10 0 05 A1 0 36 0 56 A 1 40 MAX 1 70 MAX REFERENCE JEDEC MO 192 15 00 1 00 0 35 A 17 00 0 10 7 50 7 50 15 00 17 00 0 10 1 00 A1 0 05 0 10 256 Ball FBGA 17 x 17 mm BB256 51 85108 F Fee...

Page 60: ...Ultra37000 CPLD Family Document 38 03007 Rev E Page 60 of 64 Package Diagrams continued 292 Ball Plastic Ball Grid Array PBGA 27 x 27 x 2 33 mm BG292 51 85097 B Feedback ...

Page 61: ...Ultra37000 CPLD Family Document 38 03007 Rev E Page 61 of 64 Package Diagrams continued 51 85103 C 388 Ball Plastic Ball Grid Array PBGA 35 x 35 x 2 33 mm BG388 Feedback ...

Page 62: ...ts products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges ViewDraw and SpeedWave are trademarks of ViewL...

Page 63: ...3007 Rev E Page 63 of 64 Addendum 3 3V Operating Range CY37064VP100 143AC CY37064VP100 143BBC CY37064VP44 143AC CY37064VP48 143BAC Range Ambient Temperature 2 Junction Temperature VCC Commercial 0 C to 70 C 0 C to 90 C 3 3V 0 16V Feedback ...

Page 64: ...4 154AXI CY37032P44 154JXI CY37032P44 125AXC CY37032P44 125JXC CY37064P44 200AXC CY37064P44 200JXC CY37064P100 200AXC CY37064P44 154AXI CY37064P44 154JXI CY37064P44 125AXC CY37064P44 125JXC CY37064P100 125AXC CY37064P44 125AXI CY37064P100 125AXI CY37128P84 167JXC CY37128P100 167AXC CY37128P160 167AXC CY37128P84 125JXC CY37128P100 125AXC CY37128P160 125AXC CY37128P84 125JXI CY37128P100 125AXI CY371...

Search results

Summary of Contents for ISR 37000 CPLD

Reviews:

Related manuals for ISR 37000 CPLD

Brands by name

Popular brands

Cypress Semiconductor ISR 37000 CPLD, Specification Sheet

Search results

Summary of Contents for ISR 37000 CPLD

Reviews:

Related manuals for ISR 37000 CPLD

Brands by name

Popular brands