Cypress Semiconductor EZ-Host CY7C67300 Specification Sheet Download Page 92

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CY7C67300

Document #: 38-08015 Rev. *J

Page 92 of 99

Hardware CTS/RTS Handshake

CTSsetup

: HSS_CTS setup time before HSS_RTS = 1.5T min.

CTShold

: HSS_CTS hold time after START bit = 0 ns min.

T = 1/48 MHz.

When RTS/CTS hardware handshake is enabled, transmission can be help off by deasserting HSS_CTS at least 1.5T before
HSS_RTS. Transmission resumes when HSS_CTS returns HIGH. HSS_CTS must remain HIGH until START bit.

HSS_RTS is deasserted in the third data bit time.

An application may choose to hold HSS_CTS until HSS_RTS is deasserted, which always occurs after the START bit.

Register Summary

tCTSsetup

Start of transmission delayed until HSS_CTS goes high

Start of transmission not delayed by HSS_CTS

tCTShold

HSS_RTS

HSS_CTS

HSS_TxD

Table 142. Register Summary

R/W

Address

Register

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default High

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default Low

0x0140

HPI Breakpoint

Address...

0000 0000

...Address

0000 0000

0x0142

Interrupt Routing

VBUS to HPI
Enable

ID to HPI
Enable

SOF/EOP2 to
HPI Enable

SOF/EOP2 to
CPU Enable

SOF/EOP1 to
HPI Enable

SOF/EOP1 to
CPU Enable

Reset2 to HPI
Enable

HPI Swap 1
Enable

0001 0100

Resume2 to
HPI Enable

Resume1 to
HPI Enable

Reserved

Done2 to HPI
Enable

Done1 to HPI
Enable

Reset1 to HPI
Enable

HPI Swap 0
Enable

0000 0000

1: 0x0144
2: 0x0148

SIEXmsg

Data...

xxxx xxxx

...Data

xxxx xxxx

R/W

0x02n0

Device n Endpoint n Control

Reserved

xxxx xxxx

IN/OUT
Ignore Enable

Sequence
Select

Stall
Enable

ISO
Enable

NAK Interrupt
Enable

Direction
Select

Enable

ARM
Enable

xxxx xxxx

R/W

0x02n2

Device n Endpoint n Address

Address...

xxxx xxxx

...Address

xxxx xxxx

R.W

0x02n4

Device n Endpoint n Count

Reserved

Count...

xxxx xxxx

...Count

xxxx xxxx

R/W

0x02n6

Device n Endpoint n Status

Reserved

Overflow
Flag

Underflow
Flag

OUT
Exception Flag

IN
Exception Flag

xxxx xxxx

Stall
Flag

NAK
Flag

Length
Exception Flag

Setup
Flag

Sequence
Status

Timeout
Flag

Error
Flag

ACK
Flag

xxxx xxxx

R/W

0x02n8

Device n Endpoint n Count Result Result...

xxxx xxxx

...Result

xxxx xxxx

0xC000

CPU Flags

Reserved...

0000 0000

...Reserved

Global Inter-
rupt Enable

Negative
Flag

Overflow
Flag

Carry
Flag

Zero
Flag

000x xxxx

R/W

0xC002

Bank

Address...

0000 0001

...Address

Reserved

000x xxxx

0xC004

Hardware Revision

Revision...

xxxx xxxx

...Revision

xxxx xxxx

R/W

0xC006

GPIO Control

Write Protect
Enable

Reserved

SAS
Enable

Mode
Select

0000 0000

HSS
Enable

HSS XD
Enable

SPI
Enable

SPI XD
Enable

Interrupt 1
Polarity
Select

Interrupt 1
Enable

Interrupt 0
Polarity
Select

Interrupt 0
Enable

0000 0000

R/W

0xC008

CPU Speed

Reserved...

0000 0000

.Reserved

CPU Speed

0000 1111

R/W

0xC00A

Power Control

Host/Device
2B Wake
Enable

Host/Device
2A Wake
Enable

Host/Device
1B Wake
Enable

Host/Device
1A Wake
Enable

OTG
Wake
Enable

Reserved

HSS
Wake
Enable

SPI
Wake
Enable

0000 0000

HPI
Wake Enable

Reserved

GPI
Wake Enable

Reserved

Boost 3V
OK

Sleep
Enable

Halt
Enable

0000 0000

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Summary of Contents for EZ-Host CY7C67300

Page 1: ...I with a DMA mailbox data path for an external processor to directly access all of the on chip memory and control on chip SIEs Fast serial port supports from 9600 baud to 2 0M baud SPI support in both...

Page 2: ...Watchdog Timer EZ Host has two built in programmable timers and a Watchdog timer All three timers can generate an interrupt to the EZ Host Power Management EZ Host has one main power saving mode Slee...

Page 3: ...Host and Peripheral ports simultaneously as shown in Table 3 GPIO10 D10 D10 SCK 1 GPIO9 D9 D9 nSSI 1 GPIO8 D8 D8 MISO 1 GPIO7 D7 D7 GPIO6 D6 D6 GPIO5 D5 D5 GPIO4 D4 D4 GPIO3 D3 D3 GPIO2 D2 D2 GPIO1 D1...

Page 4: ...hable 2K ohm internal discharge resistor on VBUS Switchable 500 ohm internal pull up resistor on VBUS Individually switchable internal pull up and pull down resistors on the USB data lines OTG Pins 2...

Page 5: ...XRAMSEL is active from 0x4000 to 0xBFFF when RAM Merge is enabled nXROMSEL is active from 0xC100 to 0xDFFF when ROM Merge is disabled nXROMSEL is active from 0x8000 to 0xDFFF excluding the 0xC000 to 0...

Page 6: ...SEL ROM nCS 35 nXRAMSEL RAM nCS 36 A18 95 A17 96 A16 97 A15 38 A14 33 A13 32 A12 31 A11 30 A10 27 A9 25 A8 24 A7 20 A6 17 A5 8 A4 7 A3 3 A2 2 A1 1 nBEL A0 99 nBEH 98 D15 67 D14 68 D13 69 D12 70 D11 71...

Page 7: ...general I2 C interface The I2 C EEPROM interface is a BIOS implementation and is exposed through GPIO pins Refer to the BIOS documentation for additional details on this interface I2 C EEPROM Feature...

Page 8: ...ndshake protocol Selectable XON XOFF software handshake protocol Programmable Receive interrupt Block Transfer Done inter rupts Complete access to internal memory HSS Pins The HSS port has a few diffe...

Page 9: ...shown in Table 13 IDE Interface EZ Host has an IDE interface The IDE interface supports PIO mode 0 4 as specified in the Information Technology AT Attachment 4 with Packet Interface Extension ATA ATA...

Page 10: ...be used CSWITCHA CSWITCHB and OTGVBUS can be left unconnected Charge Pump Features Meets OTG Supplement Requirements see Table 134 DC Characteristics Charge Pump on page 84 for details Charge Pump Pi...

Page 11: ...d crystal circuit to be used with EZ Host is shown in Figure 8 If an oscillator is used instead of a crystal circuit connect it to XTALIN and leave XTALOUT unconnected For further information about th...

Page 12: ...sor drives EZ Host and is the main processor rather then EZ Host s own 16 bit internal CPU An external host processor may interface to EZ Host through one of the following three interfaces in coproces...

Page 13: ...setting the Sleep Enable bit 1 of the Power control register 0xC00A During Sleep mode USB Suspend the following events and states are true GPIO pins maintain their configuration during sleep in suspen...

Page 14: ...self from 0xE000 to 0xFFFF For more information about the reserved lower memory or the BIOS ROM refer to the Programmer s documentation and or the BIOS documentation During development with the EZ Hos...

Page 15: ...Registers USER SPACE 16K USER SPACE 8K 01 Extended Page 1 USER SPACE Up to 64 8K Banks 01 Extended Page 2 USER SPACE Up to 64 8K Banks Bank Selected by 0xC018 Bank Selected by 0xC01A 0x0100 0x011F 0x...

Page 16: ...The Overflow Flag bit indicates if an overflow condition occurred An overflow condition can occur if an arithmetic result was either larger than the destination operand size for addition or smaller t...

Page 17: ...Hardware Revision Register 0xC004 R Register Description The Hardware Revision register is a read only register that indicates the silicon revision number The first silicon revision is represented by...

Page 18: ...speed of the processor as defined in Table 27 Reserved Write all reserved bits with 0 Table 26 CPU Speed Register Bit 15 14 13 12 11 10 9 8 Field Reserved Read Write Default 0 0 0 0 0 0 0 0 Bit 7 6 5...

Page 19: ...es or disables a wakeup condition to occur on either an OTG VBUS_Valid or OTG ID transition IRQ20 1 Enable wakeup on OTG VBUS valid or OTG ID transition 0 Disable wakeup on OTG VBUS valid or OTG ID tr...

Page 20: ...bits with 0 Interrupt Enable Register 0xC00E R W Register Description The Interrupt Enable register allows control of the hardware interrupt vectors OTG Interrupt Enable Bit 12 The OTG Interrupt Enab...

Page 21: ...When the GPIO bit is reset all pending GPIO interrupts are also cleared 1 Enable GPIO interrupt 0 Disable GPIO interrupt Timer 1 Interrupt Enable Bit 1 The Timer 1 Interrupt Enable bit enables or disa...

Page 22: ...the following enabled test conditions J K DCK SE0 RSF RSL PRD 0 Do not apply test conditions Pull down Enable Bit 6 The Pull down Enable bit enables or disables full speed pull down resistors pull dow...

Page 23: ...ction and are summarized in Table 35 Table 33 Memory Diagnostic Register Bit 15 14 13 12 11 10 9 8 Field Reserved Memory Arbitration Select Read Write W W W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0...

Page 24: ...C038 R W Register Description The Upper Address Enable register enables disables the four most significant bits of the external address A 18 15 This register defaults to having the Upper Address disab...

Page 25: ...it 7 The XROM Width Select bit selects the external ROM width 1 External memory 8 0 External memory 16 XROM Wait Select Bits 6 4 The XROM Wait Select field selects the external ROM wait state from 0 t...

Page 26: ...g so the Watchdog timer can be set up and enabled permanently so that it can only be cleared on reset the WDT Enable bit is ignored 1 Watchdog timer permanently set 0 Watchdog timer not permanently se...

Page 27: ...ter Description The USB n Control register is used in both host and device mode It monitors and controls the SIE and the data lines of the USB ports This register can be accessed by the HPI interface...

Page 28: ...l down resistors appropriately When the Mode Select is set for Host mode the pull down resistors on the data lines D and D are enabled When the Mode Select is set for Device mode a single pull up resi...

Page 29: ...amble Enable Bit 7 The Preamble Enable bit enables or disables the transmission of a preamble packet before all low speed packets Set this bit only when communicating with a low speed device 1 Enable...

Page 30: ...0 when a transaction is complete 1 Arm endpoint and begin transaction 0 Endpoint disarmed Reserved Write all reserved bits with 0 Host n Address Register R W Host 1 Address Register 0xC082 Host 2 Addr...

Page 31: ...Overflow condition did not occur Underflow Flag Bit 10 The Underflow Flag bit indicates that the received data in the last data transaction was less than the maximum length specified in the Host n Cou...

Page 32: ...d Underflow are not considered errors and do not affect this bit CRC5 and CRC16 errors result in an Error flag along with receiving incorrect packet types 1 Error detected 0 No error detected ACK Flag...

Page 33: ...from the value specified in the Host n Count register the Length Exception Flag bit in the Host n Endpoint Status register is set The value in this register is only value when the Length Exception Fla...

Page 34: ...he rising and falling edge of VBUS at the 4 4V status only supported in Port 1A This bit is only available for Host 1 and is a reserved bit in Host 2 1 Enable VBUS interrupt 0 Disable VBUS interrupt I...

Page 35: ...r the host responds with an ACK or a device responds with any of the following ACK NAK STALL or Timeout This interrupt is used for both Port A and Port B 1 Enable USB Transfer Done interrupt 0 Disable...

Page 36: ...onnect Change Interrupt Flag bit it can be determined whether a device was inserted non SE0 condition or removed SE0 condition 1 SE0 condition 0 Non SE0 condition Port A SE0 Status Bit 2 The Port A SE...

Page 37: ...next frame number to be transmitted current frame number 1 This value is updated after each SOF transmission This register resets to 0x0000 after each CPU write to the Host n SOF EOP Count register H...

Page 38: ...f eight endpoints for each of the two ports All endpoints have the same definition for their Device n Endpoint n Control register IN OUT Ignore Enable Bit 7 The IN OUT Ignore Enable bit forces endpoin...

Page 39: ...nt n Status register If a setup packet is received and the Direction Select bit is set incorrectly the setup is ACKed and the Setup Status Flag is set refer to the setup bit of the Device n Endpoint n...

Page 40: ...t Register Device 1 0x0254 Device 2 0x02D4 Device n Endpoint 6 Count Register Device 1 0x0264 Device 2 0x02E4 Device n Endpoint 7 Count Register Device 1 0x0274 Device 2 0x02F4 Register Description Th...

Page 41: ...low condition did not occur Underflow Flag Bit 10 The Underflow Flag bit indicates that the received data in the last data transaction was less then the maximum length specified in the Device n Endpoi...

Page 42: ...ors and do not affect this bit 1 Error occurred 0 Error did not occur ACK Flag Bit 0 The ACK Flag bit indicates whether the last transaction was ACKed 1 ACK occurred 0 ACK did not occur Device n Endpo...

Page 43: ...ort 2A is enabled Device n Interrupt Enable Register R W Device 1 Interrupt Enable Register 0xC08C Device 2 Interrupt Enable Register 0xC0AC Register Description The Device n Interrupt Enable register...

Page 44: ...terrupt 0 Disable EP6 Transaction Done interrupt EP5 Interrupt Enable Bit 5 The EP5 Interrupt Enable bit enables or disables endpoint five EP5 Transaction Done interrupt An EPx Transaction Done interr...

Page 45: ...gister Description The Device n Address register holds the device address assigned by the host This register initializes to the default address 0 at reset but must be updated by firmware when the host...

Page 46: ...pt triggered An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device s supplied EP send receive ACK send STALL Timeout occurs IN...

Page 47: ...Timeout occurs IN Exception Error or OUT Exception Error In addition if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set this interrupt also triggers when the device NAKs...

Page 48: ...s one register dedicated for On The Go operation This register is covered in this section and summarized in Table 74 OTG Control Register 0xC098 R W Register Description The OTG Control register allow...

Page 49: ...wn resistor disabled D Pull down Enable Bit 6 The D Pull down Enable bit enables or disables a pull down resistor on the OTG D data line 1 OTG D dataline pull down resistor enabled 0 OTG D dataline pu...

Page 50: ...XD 15 12 SPI Enable Bit 5 The SPI Enable bit routes SPI to GPIO 11 8 If the SAS Enable bit is set it overrides the SPI Enable and routes SPI_nSSI to GPIO15 If the SPI XD Enable bit is set it override...

Page 51: ...Register Data Bits 15 0 The Data field 15 0 writes to the corresponding GPIO 15 0 or GPIO31 16 pins as output data GPIO n Input Data Register R GPIO 0 Input Data Register 0xC020 GPIO 1 Input Data Reg...

Page 52: ...in Table 82 IDE Mode Register 0xC048 R W Register Description The IDE Mode register allows the selection of IDE PIO Modes 0 1 2 3 or 4 The default setting is zero which means IDE PIO Mode 0 Mode Selec...

Page 53: ...ps an internal memory address counter The two MSBs of the addresses are not modified by the address counter Therefore the IDE Start Address and IDE Stop Address must reside within the same 16K byte bl...

Page 54: ...Enable Bit 2 The IDE Interrupt Enable bit enables or disables the block transfer done interrupt When enabled the Done Flag is sent to the CPU as cpuide_intr interrupt When disabled the cpuide_intr is...

Page 55: ...ress ATA ATAPI Register IDE_nCS 1 0 IDE_A 2 0 0xC050 DATA Register 10 000 0xC052 Read Error Register Write Feature Register 10 001 0xC054 Sector Count Register 10 010 0xC056 Sector Number Register 10...

Page 56: ...ket Ready inter rupts Done Interrupt Enable Bit 8 The Done Interrupt Enable bit enables or disables the Transmit Done and Receive Done interrupts 1 Enable the Transmit Done and Receive Done interrupts...

Page 57: ...ly bit that indicates if the HSS receive FIFO is full with eight bytes or not 1 HSS receive FIFO is full 0 HSS receive FIFO is not full Receive Ready Flag Bit 0 The Receive Ready Flag is a read only b...

Page 58: ...ceived on the HSS port not for block receive mode when read This receive data is valid when the Receive Ready bit of the HSS Control register is set to 1 Writing to this register initiates a single by...

Page 59: ...is decremented When read this register indicates the remaining length of the transfer Counter Bits 9 0 The Counter field value is equal to the word count minus one giving a maximum value of 0x03FF 102...

Page 60: ...lue is decremented When read this register indicates the remaining length of the transfer Counter Bits 9 0 The Counter field value is equal to the word count minus one giving a maximum value of 0x03FF...

Page 61: ...PU but is read write by the HPI port By setting the appropriate bit to 1 the SIE interrupt is routed to the HPI port to become the HPI_INTR signal and also readable in the HPI Status register The bits...

Page 62: ...to identical values When set to 00 the most significant data byte goes to HPI_D 15 8 and the least significant byte goes to HPI_D 7 0 This is the default setting By setting to 11 the most significant...

Page 63: ...ilbox RX Full interrupt is automatically cleared If enabled the HPI Mailbox TX Empty interrupt triggers when the external host processor reads from this register The HPI Mailbox TX Empty interrupt aut...

Page 64: ...indicates if a message is ready in the incoming mailbox This interrupt clears when the on chip CPU reads from the HPI Mailbox register 1 Interrupt triggered 0 Interrupt did not trigger Resume2 Flag Bi...

Page 65: ...ly bit that indicates if a message is ready in the outgoing mailbox This interrupt clears when the external host reads from the HPI Mailbox register 1 Interrupt triggered 0 Interrupt did not trigger S...

Page 66: ...it is only writable when the Master Active Enable bit reads 0 otherwise the value does not change 1 Master SPI interface 0 Slave SPI interface SS Enable Bit 5 The SS Enable bit enables or disables the...

Page 67: ...sets the slave to receive in slave mode 1 Initiates a read phase for a master transfer or sets a slave to receive In master mode this bit is sticky and remains set until the read transfer begins 0 Ini...

Page 68: ...nterrupt Reserved Write all reserved bits with 0 SPI Status Register 0xC0CE R Register Description The SPI Status register is a read only register that provides status for the SPI port FIFO Error Flag...

Page 69: ...The Transmit Interrupt Clear bit is a write only bit that clears the byte mode transmit interrupt This bit is self clearing 1 Clear the byte mode transmit interrupt 0 No function Transfer Interrupt C...

Page 70: ...not all zeros 0 CRC value is all zeros Zero in CRC Bit 9 The Zero in CRC bit is a read only bit that indicates if the CRC value is all ones or not 1 CRC value is not all ones 0 CRC value is all ones R...

Page 71: ...field contains data received or to be transmitted on the SPI port Reserved Write all reserved bits with 0 SPI Transmit Address Register 0xC0D8 R W Register Description The SPI Transmit Address registe...

Page 72: ...A SPI Receive Count Register 0xC0DE R W Table 116 SPI Transmit Count Register Bit 15 14 13 12 11 10 9 8 Field Reserved Count Read Write R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Co...

Page 73: ...e by eight 1 Enable prescaler 0 Disable prescaler Baud Select Bits 3 1 Refer to Table 121 for a definition of this field UART Enable Bit 0 The UART Enable bit enables or disables the UART 1 Enable UAR...

Page 74: ...This bit is automatically cleared to 0 after the data is transmitted 1 Transmit buffer full transmit busy 0 Transmit buffer is empty and ready for a new byte of data UART Data Register 0xC0E4 R W Regi...

Page 75: ...8 R W PWM0 Start Register 0xC0EA R W PWM0 Stop Register 0xC0EC R W PWM1 Start Register 0xC0EE R W PWM1 Stop Register 0xC0F0 R W PWM2 Start Register 0xC0F2 R W PWM2 Stop Register 0xC0F4 R W PWM3 Start...

Page 76: ...LOW PWM 0 Polarity Select Bit 4 The PWM 0 Polarity Select bit selects the polarity for PWM 0 1 Sets the polarity to active HIGH or rising edge pulse 0 Sets the polarity to active LOW PWM 3 Enable Bit...

Page 77: ...iption The PWM n Stop register designates where in the window defined by the PWM Maximum Count register to stop the PWM pulse for a supplied channel Address Bits 9 0 The Address field designates when...

Page 78: ...PWM Control register to 1 Count Bits 9 0 The Count field designates the number of cycles plus one to run when in one shot mode For example Cycles PWM Cycle Count 1 therefore for two cycles set PWM Cyc...

Page 79: ...D nBEL A0 nBEH A16 A17 A18 GPIO0 D0 GPIO1 D1 GPIO2 D2 GPIO3 D3 GPIO4 D4 GPIO5 D5 VCC GPIO6 D6 GPIO7 D7 nRESET Reserved D0 D1 D2 D4 D5 D6 D7 D3 GND GPIO19 A0 CS0 GPIO18 A2 RTS PWM2 GPIO17 A1 RXD PWM1 G...

Page 80: ...t A0 for 0 8 bit memories 98 nBEH Output High Byte Enable for 16 bit memories 64 nWR Output External Memory Write pulse 62 nRD Output External Memory Read pulse 97 A16 Output A16 External SRAM A16 96...

Page 81: ...7 GPIO23 nRD IOR IO GPIO23 General Purpose IO nRD HPI nRD IOR IDE IOR 48 GPIO22 nWR IOW IO GPIO22 General Purpose IO nWR HPI nWR IOW IDE IOW 49 GPIO21 nCS IO GPIO21 General Purpose IO nCS HPI nCS 50 G...

Page 82: ...IO1 D1 IO GPIO1 General Purpose IO D1 D1 for HPI or IDE 94 GPIO0 D0 IO GPIO0 General Purpose IO D0 D0 for HPI or IDE 22 DM1A IO USB Port 1A D 23 DP1A IO USB Port 1A D 18 DM1B IO USB Port 1B D 19 DP1B...

Page 83: ...UT DC Characteristics Notes 7 The on chip voltage booster circuit boosts BoostVCC to provide a nominal 3 3V VCC supply 8 All tests were conducted with Charge pump off Table 132 Crystal Requirements Cr...

Page 84: ...mA ILOAD 10 mA 4 4 5 25 V TA_VBUS_RISE VBUS Rise Time ILOAD 10 mA 100 ms IA_VBUS_OUT Maximum Load Current 8 10 mA CDRD_VBUS OUTVBUS Bypass Capacitance 4 4V VBUS 5 25V 1 0 6 5 pF VA_VBUS_LKG OTGVBUS L...

Page 85: ...16 clocks 11 tIOACT nRESET HIGH to nRD or nWRx active 200 s nRESET nRD or nWRL or nWRH tRESET tIOACT Reset Timing Table 136 Clock Timing Parameters Parameter Description Min Typical Max Unit fCLK Clo...

Page 86: ...n 1 T 48 MHz clock period 15 Read timing is applicable for nXMEMSEL nXRAMSEL and nXROMSEL Table 137 SRAM Read Cycle Parameters Parameter Description Min Typical Max Unit tCR CS LOW to RD LOW 1 ns tRDH...

Page 87: ...k period 17 Write timing is applicable for nXMEMSEL nXRAMSEL and nXROMSEL Table 138 SRAM Write Cycle Parameters Parameter Description Min Typical Max Unit tAW Write Address Valid to WE LOW 7 ns tCSW C...

Page 88: ...Width High 600 ns tAA Clock Low to Data Out Valid 900 ns tBUF Bus Idle Before New Transmission 1300 ns tHD STA Start Hold Time 600 ns tSU STA Start Setup Time 600 ns tHD DAT Data In Hold Time 0 ns tSU...

Page 89: ...ycle Timing Parameters Parameter Description Min Typical Max Unit tASU Address Setup 1 ns tAH Address Hold 1 ns tCSSU Chip Select Setup 1 ns tCSH Chip Select Hold 1 ns tDSU Data Setup 6 ns tWDH Write...

Page 90: ...SU Address Setup 1 ns tAH Address Hold 1 ns tCSSU Chip Select Setup 1 ns tCSH Chip Select Hold 1 ns tACC Data Access Time from HPI_nRD falling 1 T 18 tRDH Read Data Hold relative to the earlier of HPI...

Page 91: ...coming data bit rate may deviate from the programmed baud rate clock by as much as 5 with HSS_RATE value of 23 or higher BYTE mode received bytes are buffered in a FIFO The FIFO not empty condition be...

Page 92: ...xxxx xxxx Data xxxx xxxx R W 0x02n0 Device n Endpoint n Control Reserved xxxx xxxx IN OUT Ignore Enable Sequence Select Stall Enable ISO Enable NAK Interrupt Enable Direction Select Enable ARM Enable...

Page 93: ...lect XRAM Wait Select xxxx xxxx R W 0xC03C USB Diagnostic Port 2B Diagnostic Enable Port 2A Diagnostic Enable Port 1B Diagnostic Enable Port 1A Diagnostic Enable Reserved 0000 0000 Reserved Pull down...

Page 94: ...In terrupt En able Reserved SOF EOP Interrupt Enable Reset Interrupt Enable 0000 0000 EP7 Interrupt Enable EP6 Interrupt Enable EP5 Interrupt Enable EP4 Interrupt Enable EP3 Interrupt Enable EP2 Inte...

Page 95: ...er rupt Enable Transmit Inter rupt Enable Transfer Inter rupt Enable 0000 0000 R 0xC0CE SPI Status Reserved 0000 0000 FIFO Error Flag Reserved Receive Interrupt Flag Transmit Interrupt Flag Transfer I...

Page 96: ...00 R HPI Status Port VBUS Flag ID Flag Reserved SOF EOP2 Flag Reserved SOF EOP1 Flag Reset2 Flag Mailbox In Flag Resume2 Flag Resume1 Flag SIE2msg SIE1msg Done2 Flag Done1 Flag Reset1 Flag Mailbox Out...

Page 97: ...elopment Kit NOTE 1 JEDEC STD REF MS 026 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE 3 DIMENSIONS IN MILLIM...

Page 98: ...p Section and added CLKSEL to Pin Description Added USB OTG Logo General Clean up F 443992 VCS See ECN Title changed indicating AEC Grade Added information for AEC qualified including part number Fixe...

Page 99: ...erable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of lic...

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