CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Document Number: 38-12025 Rev. *O
Page 33 of 45
Figure 19. Definition for Timing for Fast/Standard Mode on the I
2
C Bus
Table 39. 2.7V AC Characteristics of the I
2
C SDA and SCL Pins (Fast Mode not Supported)
Symbol
Description
Standard Mode
Fast Mode
Units
Min
Max
Min
Max
F
SCLI2C
SCL Clock Frequency
0
100
–
–
kHz
T
HDSTAI2C
Hold Time (repeated) START Condition.
After this period, the first clock pulse is
generated.
4.0
–
–
–
μ
s
T
LOWI2C
LOW Period of the SCL Clock
4.7
–
–
–
μ
s
T
HIGHI2C
HIGH Period of the SCL Clock
4.0
–
–
–
μ
s
T
SUSTAI2C
Set up Time for a Repeated START
Condition
4.7
–
–
–
μ
s
T
HDDATI2C
Data Hold Time
0
–
–
–
μ
s
T
SUDATI2C
Data Set-up Time
250
–
–
–
ns
T
SUSTOI2C
Set up Time for STOP Condition
4.0
–
–
–
μ
s
T
BUFI2C
Bus Free Time Between a STOP and START
Condition
4.7
–
–
–
μ
s
T
SPI2C
Pulse Width of spikes are suppressed by the
input filter.
–
–
–
–
ns
SDA
SCL
S
Sr
S
P
T
BUFI2C
T
SPI2C
T
HDSTAI2C
T
SUSTOI2C
T
SUSTAI2C
T
LOWI2C
T
HIGHI2C
T
HDDATI2C
T
HDSTAI2C
T
SUDATI2C
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