Cypress Semiconductor CY8C21234, Specification Sheet

Page: 29 / 45

CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Document Number: 38-12025 Rev. *O Page 29 of 45
AC Analog Mux Bus Specifications
Table 31 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40 ° C
≤
T
A
≤
85 ° C, 3.0V to 3.6V and -40 ° C
≤
T
A
≤
85 ° C, or 2.4V to 3.0V and -40 ° C
≤
T
A
≤
85 ° C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25 ° C and are for design guidance only.
AC Digital Block Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40 ° C
≤
T
A
≤
85 ° C, 3.0V to 3.6V and -40 ° C
≤
T
A
≤
85 ° C, or 2.4V to 3.0V and -40 ° C
≤
T
A
≤
85 ° C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25 ° C and are for design guidance only.
Table 31. AC Analog Mux Bus Specifications
Symbol Description Min Typ Max Units Notes
F
SW
Switch Rate – – 3.17 MHz
Table 32. 5V and 3.3V AC Digital Block Specifications
Function Description Min Typ Max Units Notes
All
Functions
Maximum Block Clocking Frequency (> 4.75V) 49.2 MHz 4.75V < Vdd < 5.25V.
Maximum Block Clocking Frequency (< 4.75V) 24.6 MHz 3.0V < Vdd < 4.75V.
Timer Capture Pulse Width 50
[19]
– – ns
Maximum Frequency, No Capture – – 49.2 MHz 4.75V < Vdd < 5.25V.
Maximum Frequency, With or Without Capture – – 24.6 MHz
Counter Enable Pulse Width 50 – – ns
Maximum Frequency, No Enable Input – – 49.2 MHz 4.75V < Vdd < 5.25V.
Maximum Frequency, Enable Input – – 24.6 MHz
Dead Band Kill Pulse Width:
Asynchronous Restart Mode 20 – – ns
Synchronous Restart Mode 50 – – ns
Disable Mode 50 – – ns
Maximum Frequency – – 49.2 MHz 4.75V < Vdd < 5.25V.
CRCPRS
(PRS
Mode)
Maximum Input Clock Frequency – – 49.2 MHz 4.75V < Vdd < 5.25V.
CRCPRS
(CRC
Mode)
Maximum Input Clock Frequency – – 24.6 MHz
SPIM Maximum Input Clock Frequency – – 8.2 MHz Maximum data rate at 4.1 MHz
due to 2 x over clocking.
SPIS Maximum Input Clock Frequency – – 4.1 MHz
Width of SS_ Negated Between Transmissions 50 – – ns
Transmitter Maximum Input Clock Frequency
Maximum Input Clock Frequency with Vdd
≥
4.75V, 2 Stop Bits
–
–
–
–
24.6
49.2
MHz
MHz
Maximum data rate at 3.08 MHz
due to 8 x over clocking.
Maximum data rate at 6.15 MHz
due to 8 x over clocking.
Receiver Maximum Input Clock Frequency
Maximum Input Clock Frequency with Vdd
≥
4.75V, 2 Stop Bits
–
–
–
–
24.6
49.2
MHz
MHz
Maximum data rate at 3.08 MHz
due to 8 x over clocking.
Maximum data rate at 6.15 MHz
due to 8 x over clocking.
Note
19. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
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