CY7C1411JV18, CY7C1426JV18
CY7C1413JV18, CY7C1415JV18
Document Number: 001-12557 Rev. *C
Page 2 of 28
Logic Block Diagram (CY7C1411JV18)
Logic Block Diagram (CY7C1426JV18)
1M x 8 A
rr
a
y
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
D
[7:0]
Read Add
. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
16
20
32
8
NWS
[1:0]
V
REF
W
rite Add. D
e
co
de
Write
Reg
16
A
(20:0)
20
8
CQ
CQ
DOFF
Q
[7:0]
8
8
8
Write
Reg
Write
Reg
Write
Reg
C
C
1M x 8 A
rr
a
y
1M x 8 A
rr
a
y
1M x 8 A
rr
a
y
8
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
D
[8:0]
Read
A
d
d. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
20
36
9
BWS
[0]
V
REF
W
rite Add.
Decode
Write
Reg
18
A
(19:0)
20
9
CQ
CQ
DOFF
Q
[8:0]
9
9
9
Write
Reg
Write
Reg
Write
Reg
C
C
1
M
x 9 Arra
y
1
M
x 9 Arra
y
1
M
x 9 Arra
y
1
M
x 9 Arra
y
9
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