Cypress Semiconductor CY7C1411JV18 Specification Sheet Download Page 25

Page: 25 / 28

CY7C1411JV18, CY7C1426JV18

CY7C1413JV18, CY7C1415JV18

Document Number: 001-12557 Rev. *C

Page 25 of 28

Ordering Information

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or
visit

www.cypress.com

for actual products offered.

Speed

(MHz)

Ordering Code

Package
Diagram

Package Type

Operating

Range

300

CY7C1411JV18-300BZC

51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)

Commercial

CY7C1426JV18-300BZC

CY7C1413JV18-300BZC

CY7C1415JV18-300BZC

CY7C1411JV18-300BZXC

51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1426JV18-300BZXC

CY7C1413JV18-300BZXC

CY7C1415JV18-300BZXC

CY7C1411JV18-300BZI

51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)

Industrial

CY7C1426JV18-300BZI

CY7C1413JV18-300BZI

CY7C1415JV18-300BZI

CY7C1411JV18-300BZXI

51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1426JV18-300BZXI

CY7C1413JV18-300BZXI

CY7C1415JV18-300BZXI

250

CY7C1411JV18-250BZC

51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)

Commercial

CY7C1426JV18-250BZC

CY7C1413JV18-250BZC

CY7C1415JV18-250BZC

CY7C1411JV18-250BZXC

51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1426JV18-250BZXC

CY7C1413JV18-250BZXC

CY7C1415JV18-250BZXC

CY7C1411JV18-250BZI

51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)

Industrial

CY7C1426JV18-250BZI

CY7C1413JV18-250BZI

CY7C1415JV18-250BZI

CY7C1411JV18-250BZXI

51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1426JV18-250BZXI

CY7C1413JV18-250BZXI

CY7C1415JV18-250BZXI

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Summary of Contents for CY7C1411JV18

Page 1: ...CY7C1415JV18 are 1 8V Synchronous Pipelined SRAMs equipped with QDR II architecture QDR II architecture consists of two separate ports to access the memory array The read port has dedicated data outp...

Page 2: ...r Reg Reg Reg 16 20 32 8 NWS 1 0 VREF Write Add Decode Write Reg 16 A 20 0 20 8 CQ CQ DOFF Q 7 0 8 8 8 Write Reg Write Reg Write Reg C C 1M x 8 Array 1M x 8 Array 1M x 8 Array 8 CLK A 19 0 Gen K K Con...

Page 3: ...VREF Write Add Decode Write Reg 36 A 18 0 19 18 CQ CQ DOFF Q 17 0 18 18 18 Write Reg Write Reg Write Reg C C 512K x 18 Array 512K x 18 Array 512K x 18 Array 512K x 18 Array 18 256K x 36 Array CLK A 1...

Page 4: ...VSS VSS VSS VDDQ NC NC Q0 M NC NC NC VSS VSS VSS VSS VSS NC NC D0 N NC D7 NC VSS A A A VSS NC NC NC P NC NC Q7 A A C A A NC NC NC R TDO TCK A A A C A A A TMS TDI CY7C1426JV18 4M x 9 1 2 3 4 5 6 7 8 9...

Page 5: ...A A C A A NC D0 Q0 R TDO TCK A A A C A A A TMS TDI CY7C1415JV18 1M x 36 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 288M NC 72M WPS BWS2 K BWS1 RPS A NC 144M CQ B Q27 Q18 D18 A BWS3 K BWS0 A D17 Q17 Q8 C D27 Q28...

Page 6: ...x 8 for CY7C1411JV18 4M x 9 4 arrays each of 1M x 9 for CY7C1426JV18 2M x 18 4 arrays each of 512K x 18 for CY7C1413JV18 and 1M x 36 4 arrays each of 256K x 36 for CY7C1415JV18 Therefore only 20 addre...

Page 7: ...GND or left unconnected DOFF Input DLL Turn Off Active LOW Connecting this pin to ground turns off the DLL inside the device The timings in the DLL turned off operation differs from those listed in th...

Page 8: ...ry other K clock rise Doing so pipelines the data flow such that data is transferred out of the device on every rising edge of the output clocks C and C or K and K when in single clock mode When the r...

Page 9: ...impedance matching with a tolerance of 15 is between 175 and 350 with VDDQ 1 5V The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperatur...

Page 10: ...data portion of a write sequence CY7C1411JV18 only the upper nibble D 7 4 is written into the device D 3 0 remains unaltered CY7C1413JV18 only the upper byte D 17 9 is written into the device D 8 0 r...

Page 11: ...into the device D 35 9 remains unaltered L H H H L H During the data portion of a write sequence only the lower byte D 8 0 is written into the device D 35 9 remains unaltered H L H H L H During the d...

Page 12: ...ling edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP...

Page 13: ...scan register After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD pl...

Page 14: ...ntroller follows 11 TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 SELECT IR S...

Page 15: ...t HIGH Voltage 0 65VDD VDD 0 3 V VIL Input LOW Voltage 0 3 0 35VDD V IX Input and Output Load Current GND VI VDD 5 5 A 0 0 1 2 29 30 31 Boundary Scan Register Identification Register 0 1 2 108 0 1 2 I...

Page 16: ...tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions...

Page 17: ...Instruction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and T...

Page 18: ...L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P...

Page 19: ...lock K K for 1024 cycles to lock the DLL DLL Constraints DLL uses K clock as its synchronizing input The input must have low phase jitter which is specified as tKC Var The DLL functions at frequencies...

Page 20: ...t HIGH Voltage Note 18 VDDQ 2 0 12 VDDQ 2 0 12 V VOL Output LOW Voltage Note 19 VDDQ 2 0 12 VDDQ 2 0 12 V VOH LOW Output HIGH Voltage IOH 0 1 mA Nominal Impedance VDDQ 0 2 VDDQ V VOL LOW Output LOW Vo...

Page 21: ...18 355 x36 395 250 MHz x8 355 mA x9 355 x18 355 x36 370 200 MHz x8 300 mA x9 300 x18 300 x36 300 AC Electrical Characteristics Over the Operating Range 13 Parameter Description Test Conditions Min Typ...

Page 22: ...unction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA JESD51 17 2 C W JC Thermal Resistance Junction to Case 3 2 C W Fig...

Page 23: ...45 0 45 0 45 ns tDOH tCHQX Data Output Hold after Output C C Clock Rise Active to Active 0 45 0 45 0 45 ns tCCQO tCHCQV C C Clock Rise to Echo Clock Valid 0 45 0 45 0 45 ns tCQOH tCHCQX Echo Clock Hol...

Page 24: ...tCQD tCLZ DOH tCHZ t t tKL tCYC tCCQO t CCQO tCQOH tCQOH KHKH KH Q00 Q03 Q01 Q02 Q20 Q23 Q21 Q22 tCO tCQDOH t tCQH tCQHCQH D10 D11 D12 D13 t SD tHD tSD tHD D30 D31 D32 D33 Notes 27 Q00 refers to outp...

Page 25: ...all Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Industrial CY7C1426JV18 300BZI CY7C1413JV18 300BZI CY7C1415JV18 300BZI CY7C1411JV18 300BZXI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 m...

Page 26: ...5JV18 200BZXC CY7C1411JV18 200BZI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Industrial CY7C1426JV18 200BZI CY7C1413JV18 200BZI CY7C1415JV18 200BZI CY7C1411JV18 200BZXI 51 85195 165...

Page 27: ...JV18 CY7C1415JV18 Document Number 001 12557 Rev C Page 27 of 28 Package Diagram Figure 6 165 Ball FBGA 15 x 17 x 1 40 mm 51 85195 0 2 2 8 8 8 3 4 0 0 2 2 4 0 6 7 44 6 7 0 2 0 2 3 2 0 490 3 2 3 3 4 3 0...

Page 28: ...RD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the...

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