Cypress Semiconductor CY7C1386D Specification Sheet Download Page 23

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CY7C1386D, CY7C1386F

CY7C1387D, CY7C1387F

Document Number: 38-05545 Rev. *E

Page 23 of 30

Read/Write Cycle Timing

[26, 28, 29]

Switching Waveforms

(continued)

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

Data Out (Q)

High-Z

ADV

Single WRITE

D(A3)

D(A5)

D(A6)

Data In (D)

BURST READ

Back-to-Back READs

High-Z

Q(A2)

Q(A1)

Q(A4)

tWEH

tWES

Q(A4+3)

tOEHZ

tDH

tDS

tOELZ

tCLZ

tCO

Back-to-Back

WRITEs

BWE, BW

DON’T CARE

UNDEFINED

Notes

28. The data bus (Q) remains in high-Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC.
29. GW is HIGH.

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Summary of Contents for CY7C1386D

Page 1: ...ning chip enable CE1 depth expansion chip enables CE2 and CE3 2 burst control inputs ADSC ADSP and ADV write enables BWX and BWE and global write GW Asynchronous inputs include the output enable OE an...

Page 2: ...BLE OUTPUT REGISTERS SENSE AMPS MEMORY ARRAY OUTPUT BUFFERS DQA DQP A BYTE WRITE DRIVER DQB DQP B BYTE WRITE DRIVER DQc DQP C BYTE WRITE DRIVER DQD DQP D BYTE WRITE DRIVER INPUT REGISTERS A0 A1 A A 1...

Page 3: ...67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 MODE CY7C1386D 512K X 36 NC A A A A A 1 A 0 NC 72M NC 36M V SS V DD A A A A A A A A A N...

Page 4: ...DQD DQD DQD DQD ADSC NC CE1 OE ADV GW VSS VSS VSS VSS VSS VSS VSS VSS DQPA MODE DQPD DQPB BWB BWC NC VDD NC BWA NC BWE BWD ZZ 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R T U VDDQ NC 288M NC 144M NC DQ...

Page 5: ...DQB DQB DQB NC DQB NC DQA DQA VDD VDDQ VDD VDDQ DQB VDD NC VDD DQA VDD VDDQ DQA VDDQ VDD VDD VDDQ VDD VDDQ DQA VDDQ A A VSS A A A DQB DQB DQB ZZ DQA DQA DQPA DQA A VDDQ A CY7C1387D 1M x 18 A0 A VSS 2...

Page 6: ...ocument for BGA CE3 is sampled only when a new external address is loaded OE Input Asynchronous Output enable asynchronous input active LOW Controls the direction of the IO pins When LOW the IO pins b...

Page 7: ...ion occurs when the SRAM is emerging from a deselected state to a selected state its outputs are always tri stated during the first cycle of the access After the first cycle of the access the outputs...

Page 8: ...synchronous self timed write mechanism has been provided to simplify the write operations The CY7C1386D CY7C1387D CY7C1386F CY7C1387F is a common IO device the output enable OE must be deasserted HIGH...

Page 9: ...ite Cycle Continue Burst Next H X X L X H L L X L H D Read Cycle Suspend Burst Current X X X L H H H H L L H Q Read Cycle Suspend Burst Current X X X L H H H H H L H Tri State Read Cycle Suspend Burst...

Page 10: ...nd DQPD H L L H H H Write Bytes D A H L L H H L Write Bytes D B H L L H L H Write Bytes D B A H L L H L L Write Bytes D C H L L L H H Write Bytes D C A H L L L H L Write Bytes D C B H L L L L H Write...

Page 11: ...nconnected if the TAP is unused in an application TDI is connected to the most signif icant bit MSB of any register See TAP Controller Block Diagram Test Data Out TDO The TDO output ball is used to se...

Page 12: ...ls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instruction register upon power up or whenever the...

Page 13: ...hese instructions are not implemented but are reserved for future use Do not use these instructions TAP Timing TAP AC Switching Characteristics Over the Operating Range 10 11 Parameter Description Min...

Page 14: ...quivalent TDO 1 5V 20pF Z 50 O 50 TDO 1 25V 20pF Z 50 O 50 TAP DC Electrical Characteristics And Operating Conditions 0 C TA 70 C VDD 3 3V 0 165V unless otherwise noted 12 Parameter Description Test C...

Page 15: ...5 85 Boundary Scan Order 165 ball FBGA package 89 89 Identification Codes Instruction Code Description EXTEST 000 Captures IO ring contents Places the boundary scan register between TDI and TDO Forces...

Page 16: ...K1 6 L5 28 E6 50 B3 72 L2 7 R6 29 D6 51 A3 73 N2 8 U6 30 C7 52 C2 74 P2 9 R7 31 B7 53 A2 75 R3 10 T7 32 C6 54 B1 76 T1 11 P6 33 A6 55 C1 77 R1 12 N7 34 C5 56 D2 78 T2 13 M6 35 B5 57 E1 79 L3 14 L7 36...

Page 17: ...67 H3 8 P9 38 B9 68 J1 9 P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46 B5 76 N1 17 J11 47 A5 77 N2 18 M1...

Page 18: ...r 3 3V IO 2 0 VDD 0 3V V for 2 5V IO 1 7 VDD 0 3V V VIL Input LOW Voltage 17 for 3 3V IO 0 3 0 8 V for 2 5V IO 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 A Input Current of...

Page 19: ...Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA JESD51 28 66 23 8 20 7 C W JC Thermal Resistance Junction to Cas...

Page 20: ...5 ns Hold Times tAH Address Hold After CLK Rise 0 3 0 4 0 5 ns tADH ADSP ADSC Hold After CLK Rise 0 3 0 4 0 5 ns tADVH ADV Hold After CLK Rise 0 3 0 4 0 5 ns tWEH GW BWE BWX Hold After CLK Rise 0 3 0...

Page 21: ...h Z tDOH tCO ADV tOEHZ tCO SingleREAD BURSTREAD tOEV tOELZ tCHZ Burstwrapsaround toitsinitialstate tADVH tADVS tWEH tWES tADH tADS Q A2 Q A2 1 Q A2 2 Q A1 Q A2 Q A2 1 Q A3 Q A2 3 A2 A3 Deselect cycle...

Page 22: ...ST READ BURST WRITE D A2 D A2 1 D A3 D A3 1 D A2 3 A2 A3 Extended BURST WRITE Single WRITE tADH tADS tADH tADS t OEHZ tADVH tADVS tWEH tWES t DH t DS GW tWEH tWES Byte write signals are ignored for rs...

Page 23: ...SC CE tAH tAS A2 tCEH tCES Data Out Q High Z ADV Single WRITE D A3 A4 A5 A6 D A5 D A6 Data In D BURST READ Back to Back READs High Z Q A2 Q A1 Q A4 tWEH tWES Q A4 3 tOEHZ tDH tDS tOELZ tCLZ tCO Back t...

Page 24: ...nued t ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS except ZZ DON T CARE I DDZZ t ZZI tRZZI Outputs Q High Z DESELECT or READ Only Notes 30 Device must be deselected when entering ZZ sleep mode See cycle des...

Page 25: ...119 ball Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1387F 167BGXI CY7C1386D 167BZI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1387D 167BZI CY7C1386D 167BZXI 51 85180 165 ball...

Page 26: ...3 x 15 x 1 4 mm Pb Free CY7C1387D 250BZXC CY7C1386D 250AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Industrial CY7C1387D 250AXI CY7C1386F 250BGI 51 85115 119 ball Ball Grid Array...

Page 27: ...PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE 3 DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0 30 0 08 0 65 20 00 0 10 22 00 0...

Page 28: ...CY7C1386D CY7C1386F CY7C1387D CY7C1387F Document Number 38 05545 Rev E Page 28 of 30 Figure 2 119 Ball BGA 14 x 22 x 2 4 mm 51 85115 Package Diagrams continued 51 85115 B Feedback...

Page 29: ...is a trademark of Intel Corporation PowerPC is a trademark of IBM Corporation All product and company names mentioned in this document are the trademarks of their respective holders Figure 3 165 Ball...

Page 30: ...nd JC for BGA Package from 45 and 7 C W to 23 8 and 6 2 C W respectively Changed JA and JC for FBGA Package from 46 and 3 C W to 20 7 and 4 0 C W respectively Modified VOL VOH test conditions Removed...

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