Cypress Semiconductor CY7C1386D Specification Sheet Download Page 7

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CY7C1386D, CY7C1386F

CY7C1387D, CY7C1387F

Document Number: 38-05545 Rev. *E

Page 7 of 30

Functional Overview

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F
supports secondary cache in systems using either a linear or
interleaved burst sequence. The interleaved burst order
supports Pentium

and i486

™

processors. The linear burst

sequence is suited for processors that use a linear burst
sequence. The burst order is user selectable, and is
determined by sampling the MODE input. Accesses can be
initiated with either the processor address strobe (ADSP) or
the controller address strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BW

) inputs. A global write

enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self timed write circuitry.
Synchronous chip selects CE

, CE

[2]

and an

asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE

is HIGH.

Single Read Accesses

This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE

is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the address
register while being presented to the memory core. The
corresponding data is allowed to propagate to the input of the
output registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within t

if OE is active LOW. The only exception

occurs when the SRAM is emerging from a deselected state
to a selected state, its outputs are always tri-stated during the
first cycle of the access. After the first cycle of the access, the
outputs are controlled by the OE signal. Consecutive single
read cycles are supported.
The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F is a
double cycle deselect part. Once the SRAM is deselected at
clock rise by the chip select and either ADSP or ADSC signals,
its output will tri-state immediately after the next clock rise.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
chip select is asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.

Ground

Ground for the core of the device

SSQ

IO Ground

Ground for the IO circuitry

DDQ

IO Power Supply

Power supply for the IO circuitry

MODE

Input-

Static

Selects burst order