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CY7C1338G

Document #: 38-05521 Rev. *D

Page 4 of 17

Functional Overview

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (t

C0

) is 6.5 ns (133-MHz device). 

The CY7C1338G supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486

processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.

Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW

[A:D]

) inputs. A Global Write

Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.

Three synchronous Chip Selects (CE

1

, CE

2

, CE

3

) and an

asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE

1

is HIGH.

Single Read Accesses

A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE

1

, CE

2

, and CE

3

 are all

asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to t

CDV

 after clock

rise. ADSP is ignored if CE

1

 is HIGH.

ADSP

Input-

Synchronous

Address Strobe from Processor, sampled on the rising edge of CLK, active LOW

. When 

asserted LOW, addresses presented to the device are captured in the address registers. A

[1:0]

 are 

also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-
nized. ASDP is ignored when CE

1

 is deasserted HIGH

ADSC

Input-

Synchronous

Address Strobe from Controller, sampled on the rising edge of CLK, active LOW

. When asserted 

LOW, addresses presented to the device are captured in the address registers. A

[1:0]

 are also loaded 

into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.

ZZ

Input-

Asynchronous

ZZ “sleep” Input, active HIGH

. When asserted HIGH places the device in a non-time-critical “sleep” 

condition with data integrity preserved. During normal operation, this pin has to be low or left floating. 
ZZ pin has an internal pull-down.

DQs

I/O-

Synchronous

Bidirectional Data I/O lines

. As inputs, they feed into an on-chip data register that is triggered by 

the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified 
by the addresses presented during the previous clock rise of the read cycle. The direction of the 
pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs 
are placed in a tri-state condition.

V

DD

Power 

Supply

Power supply inputs to the core of the device

.

V

SS

Ground

Ground for the core of the device

V

DDQ

I/O Power 

Supply

Power supply for the I/O circuitry

V

SSQ

I/O Ground

Ground for the I/O circuitry

MODE

Input-

Static

Selects Burst Order

. When tied to GND selects linear burst sequence. When tied to V

DD

 or left 

floating selects interleaved burst sequence. This is a strap pin and should remain static during device 
operation. Mode Pin has an internal pull-up.

NC

No Connects

. Not Internally connected to the die.

NC/9M,
NC/18M
NC/36M
NC/72M, 
NC/144M, 
NC/288M,
NC/576M,
NC/1G

No Connects

. Not internally connected to the die. NC/9M,NC/18M,NC/36M,NC/72M, NC/144M, 

NC/288M, NC/576M and NC/1G are address expansion pins that are not internally connected to 
the die.

Pin Definitions

  (continued)

Name

I/O

Description

Summary of Contents for CY7C1338G

Page 1: ...SC ADSP and ADV Write Enables BW A D and BWE and Global Write GW Asynchronous inputs include the Output Enable OE and the ZZ pin The CY7C1338G allows either interleaved or linear burst sequences selec...

Page 2: ...VSSQ VDDQ DQA DQA NC NC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD NC A A CE 1 CE 2 BW D BW C BW B BW A CE 3 V DD V SS CLK G...

Page 3: ...put Synchronous Chip Enable 2 Input active HIGH Sampled on the rising edge of CLK Used in conjunction with CE1 and CE3 to select deselect the device CE2 is sampled only when a new external address is...

Page 4: ...f CE1 is HIGH ADSP Input Synchronous Address Strobe from Processor sampled on the rising edge of CLK active LOW When asserted LOW addresses presented to the device are captured in the address register...

Page 5: ...ince this is a common I O device the asynchronous OE input signal must be deasserted and the I Os must be tri stated prior to the presentation of data to DQs As a safety precaution the data lines are...

Page 6: ...Burst Next H X X L X H L L X L H D Read Cycle Suspend Burst Current X X X L H H H H L L H Q Read Cycle Suspend Burst Current X X X L H H H H H L H Tri State Read Cycle Suspend Burst Current H X X L X...

Page 7: ...rite Bytes C B H L H L L H Write Bytes C B A H L H L L L Write Byte D H L L H H H Write Bytes D A H L L H H L Write Bytes D B H L L H L H Write Bytes D B A H L L H L L Write Bytes D B H L L L H H Writ...

Page 8: ...I O 1 7 VDD 0 3V V VIL Input LOW Voltage 8 for 3 3V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 A Input Current of MODE Input VSS 30 A Input VDD 5...

Page 9: ...Test conditions follow standard test methods and procedures for measuringthermalimpedance per EIA JESD51 30 32 34 1 C W JC Thermal Resistance Junction to Case 6 85 14 0 C W AC Test Loads and Waveform...

Page 10: ...0 5 0 5 ns tADH ADSP ADSC Hold After CLK Rise 0 5 0 5 ns tWEH GW BWE BWX Hold After CLK Rise 0 5 0 5 ns tADVH ADV Hold After CLK Rise 0 5 0 5 ns tDH Data Input Hold After CLK Rise 0 5 0 5 ns tCEH Chi...

Page 11: ...H or CE2 is LOW or CE3 is HIGH tCYC tCL CLK tADH tADS ADDRESS t CH tAH tAS A1 tCEH tCES Data Out Q High Z tCLZ tDOH tCDV tOEHZ tCDV Single READ BURST READ tOEV tOELZ tCHZ Burst wraps around to its ini...

Page 12: ...ADDRESS t CH tAH tAS A1 tCEH tCES High Z BURST READ BURST WRITE D A2 D A2 1 D A2 1 D A1 D A3 D A3 1 D A3 2 D A2 3 A2 A3 Extended BURST WRITE D A2 2 Single WRITE tADH tADS tADH tADS t OEHZ tADVH tADVS...

Page 13: ...nitiated by ADSP or ADSC 20 GW is HIGH Timing Diagrams continued tCYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A2 tCEH tCES Single WRITE D A3 A3 A4 BURST READ Back to Back READs High Z Q A2 Q A4 Q A4 1...

Page 14: ...ed when entering ZZ mode See Cycle Descriptions table for all possible signal conditions to deselect the device 22 DQs are in high Z when exiting ZZ sleep mode Timing Diagrams continued tZZ I SUPPLY C...

Page 15: ...Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1338G 100BGC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1338G 100BGXC 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1338G 100AXI 51...

Page 16: ...here a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer...

Page 17: ...l Resistance table Removed comment on the availability of BG lead free package Updated the Ordering Information by shading and unshading MPNs as per availability C 418633 See ECN RXU Converted from Pr...

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