Cypress Semiconductor CY7C1338G Specification Sheet Download Page 13

Page: 13 / 17

CY7C1338G

Document #: 38-05521 Rev. *D

Page 13 of 17

Read/Write Timing

[17, 19, 20]

Notes:

19. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
20. GW is HIGH.

Timing Diagrams

(continued)

tCYC

CLK

tADH

tADS

ADDRESS

tAH

tAS

tCEH

tCES

Single WRITE

D(A3)

BURST READ

Back-to-Back READs

High-Z

Q(A2)

Q(A4)

Q(A4+1)

Q(A4+2)

Q(A4+3)

WEH

WES

OEHZ

tDH

tDS

tCDV

tOELZ

D(A5)

D(A6)

Q(A1)

Back-to-Back

WRITEs

DON’T CARE

UNDEFINED

ADSP

ADSC

BWE, BW

[A:D]

ADV

Data In (D)

Data Out (Q)

Summary of Contents for CY7C1338G

Page 1: ...SC ADSP and ADV Write Enables BW A D and BWE and Global Write GW Asynchronous inputs include the Output Enable OE and the ZZ pin The CY7C1338G allows either interleaved or linear burst sequences selec...

Page 2: ...VSSQ VDDQ DQA DQA NC NC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD NC A A CE 1 CE 2 BW D BW C BW B BW A CE 3 V DD V SS CLK G...

Page 3: ...put Synchronous Chip Enable 2 Input active HIGH Sampled on the rising edge of CLK Used in conjunction with CE1 and CE3 to select deselect the device CE2 is sampled only when a new external address is...

Page 4: ...f CE1 is HIGH ADSP Input Synchronous Address Strobe from Processor sampled on the rising edge of CLK active LOW When asserted LOW addresses presented to the device are captured in the address register...

Page 5: ...ince this is a common I O device the asynchronous OE input signal must be deasserted and the I Os must be tri stated prior to the presentation of data to DQs As a safety precaution the data lines are...

Page 6: ...Burst Next H X X L X H L L X L H D Read Cycle Suspend Burst Current X X X L H H H H L L H Q Read Cycle Suspend Burst Current X X X L H H H H H L H Tri State Read Cycle Suspend Burst Current H X X L X...

Page 7: ...rite Bytes C B H L H L L H Write Bytes C B A H L H L L L Write Byte D H L L H H H Write Bytes D A H L L H H L Write Bytes D B H L L H L H Write Bytes D B A H L L H L L Write Bytes D B H L L L H H Writ...

Page 8: ...I O 1 7 VDD 0 3V V VIL Input LOW Voltage 8 for 3 3V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 A Input Current of MODE Input VSS 30 A Input VDD 5...

Page 9: ...Test conditions follow standard test methods and procedures for measuringthermalimpedance per EIA JESD51 30 32 34 1 C W JC Thermal Resistance Junction to Case 6 85 14 0 C W AC Test Loads and Waveform...

Page 10: ...0 5 0 5 ns tADH ADSP ADSC Hold After CLK Rise 0 5 0 5 ns tWEH GW BWE BWX Hold After CLK Rise 0 5 0 5 ns tADVH ADV Hold After CLK Rise 0 5 0 5 ns tDH Data Input Hold After CLK Rise 0 5 0 5 ns tCEH Chi...

Page 11: ...H or CE2 is LOW or CE3 is HIGH tCYC tCL CLK tADH tADS ADDRESS t CH tAH tAS A1 tCEH tCES Data Out Q High Z tCLZ tDOH tCDV tOEHZ tCDV Single READ BURST READ tOEV tOELZ tCHZ Burst wraps around to its ini...

Page 12: ...ADDRESS t CH tAH tAS A1 tCEH tCES High Z BURST READ BURST WRITE D A2 D A2 1 D A2 1 D A1 D A3 D A3 1 D A3 2 D A2 3 A2 A3 Extended BURST WRITE D A2 2 Single WRITE tADH tADS tADH tADS t OEHZ tADVH tADVS...

Page 13: ...nitiated by ADSP or ADSC 20 GW is HIGH Timing Diagrams continued tCYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A2 tCEH tCES Single WRITE D A3 A3 A4 BURST READ Back to Back READs High Z Q A2 Q A4 Q A4 1...

Page 14: ...ed when entering ZZ mode See Cycle Descriptions table for all possible signal conditions to deselect the device 22 DQs are in high Z when exiting ZZ sleep mode Timing Diagrams continued tZZ I SUPPLY C...

Page 15: ...Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1338G 100BGC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1338G 100BGXC 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1338G 100AXI 51...

Page 16: ...here a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer...

Page 17: ...l Resistance table Removed comment on the availability of BG lead free package Updated the Ordering Information by shading and unshading MPNs as per availability C 418633 See ECN RXU Converted from Pr...

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