Cypress Semiconductor CY7C1310BV18 Specification Sheet Download Page 24 | Manualshive

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CY7C1310BV18, CY7C1910BV18
CY7C1312BV18, CY7C1314BV18

Document #: 38-05619 Rev. *F

Page 24 of 29

Switching Waveforms

Figure 5. Read/Write/Deselect Sequence

[26, 27, 28]

K

1

2

3

4

5

8

10

6

7

K

RPS

WPS

A

D

READ

READ

WRITE

WRITE

WRITE

NOP

READ

WRITE

NOP

9

A0

tKH

tKHKH

tKL

tCYC

t

tHC

tSA tHA

tSD tHD

SC

t

tSA tHA

tSD tHD

A6

A5

A3

A4

A1

A2

D30

D50

D51

D61

D31

D11

D10

D60

Q

C

C

DON’T CARE

UNDEFINED

t

CQ

CQ

tKHCH

tCO

tKHCH

tCLZ

CHZ

tKH

tKL

Q00

Q01

Q20

tKHKH

tCYC

Q21

Q40

Q41

tCQD

tDOH

tCCQO

tCQOH

tCCQO

tCQOH

tCQDOH

Notes

26. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.
27. Outputs are disabled (High-Z) one clock cycle after a NOP.
28. In this example, if address A0 = A1, then data Q00 = D10 and Q01 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.

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Summary of Contents for CY7C1310BV18

Page 1: ...two separate ports the read port and the write port to access the memory array The read port has data outputs to support read operations and the write port has data inputs to support write operations...

Page 2: ...d Data Reg RPS WPS Control Logic Address Register Reg Reg Reg 8 20 16 8 NWS 1 0 VREF Write Add Decode Write Reg 8 A 19 0 20 CQ CQ DOFF Q 7 0 8 8 8 Write Reg C C 1M x 8 Array 1M x 9 Array CLK A 19 0 Ge...

Page 3: ...RPS WPS Control Logic Address Register Reg Reg Reg 18 19 36 18 BWS 1 0 VREF Write Add Decode Write Reg 18 A 18 0 19 CQ CQ DOFF Q 17 0 18 18 18 Write Reg C C 512K x 18 Array 256K x 36 Array CLK A 17 0...

Page 4: ...SS VSS VSS VDDQ NC NC Q0 M NC NC NC VSS VSS VSS VSS VSS NC NC D0 N NC D7 NC VSS A A A VSS NC NC NC P NC NC Q7 A A C A A NC NC NC R TDO TCK A A A C A A A TMS TDI CY7C1910BV18 2M x 9 1 2 3 4 5 6 7 8 9 1...

Page 5: ...C D0 Q0 R TDO TCK A A A C A A A TMS TDI CY7C1314BV18 512K x 36 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 288M NC 72M WPS BWS2 K BWS1 RPS NC 36M NC 144M CQ B Q27 Q18 D18 A BWS3 K BWS0 A D17 Q17 Q8 C D27 Q28 D19...

Page 6: ...or CY7C1310BV18 2M x 9 2 arrays each of 1M x 9 for CY7C1910BV18 1M x 18 2 arrays each of 512K x 18 for CY7C1312BV18 and 512K x 36 2 arrays each of 256K x 36 for CY7C1314BV18 Therefore only 20 address...

Page 7: ...cted directly to VDDQ which enables the minimum impedance mode This pin cannot be connected directly to GND or left unconnected DOFF Input DLL Turn Off Active LOW Connecting this pin to ground turns o...

Page 8: ...tion between devices without the insertion of wait states in a depth expanded memory Write Operations Write operations are initiated by asserting WPS active at the rising edge of the positive input cl...

Page 9: ...to K and CQ is generated with respect to K The timing for the echo clocks is shown in the Switching Characteristics on page 23 DLL These chips use a Delay Lock Loop DLL that is designed to function b...

Page 10: ...0 is written into the device D 17 9 remains unaltered H L L H During the data portion of a write sequence CY7C1310BV18 only the upper nibble D 7 4 is written into the device D 3 0 remains unaltered CY...

Page 11: ...into the device D 35 9 remains unaltered L H H H L H During the data portion of a write sequence only the lower byte D 8 0 is written into the device D 35 9 remains unaltered H L H H L H During the da...

Page 12: ...edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Con...

Page 13: ...scan register After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD pl...

Page 14: ...oller follows 9 TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 SELECT IR SCAN...

Page 15: ...GH Voltage 0 65VDD VDD 0 3 V VIL Input LOW Voltage 0 3 0 35VDD V IX Input and Output Load Current GND VI VDD 5 5 A 0 0 1 2 29 30 31 Boundary Scan Register Identification Register 0 1 2 106 0 1 2 Instr...

Page 16: ...IH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions Figu...

Page 17: ...ruction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO T...

Page 18: ...7 2K 7 8P 34 11E 61 4B 88 1K 8 9R 35 10E 62 3A 89 2L 9 11P 36 10D 63 1H 90 3L 10 10P 37 9E 64 1A 91 1M 11 10N 38 10C 65 2B 92 1L 12 9P 39 11D 66 3B 93 3N 13 10M 40 9C 67 1C 94 3M 14 11N 41 9D 68 1B 95...

Page 19: ...K K for 1024 cycles to lock the DLL DLL Constraints DLL uses K clock as its synchronizing input The input must have low phase jitter which is specified as tKC Var The DLL functions at frequencies dow...

Page 20: ...HIGH Voltage Note 16 VDDQ 2 0 12 VDDQ 2 0 12 V VOL Output LOW Voltage Note 17 VDDQ 2 0 12 VDDQ 2 0 12 V VOH LOW Output HIGH Voltage IOH 0 1 mA Nominal Impedance VDDQ 0 2 VDDQ V VOL LOW Output LOW Volt...

Page 21: ...00 x36 450 200 MHz x8 380 mA x9 380 x18 380 x36 400 167 MHz x8 360 mA x9 360 x18 360 x36 370 AC Electrical Characteristics Over the Operating Range 11 Parameter Description Test Conditions Min Typ Max...

Page 22: ...tion to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA JESD51 18 7 C W JC Thermal Resistance Junction to Case 4 5 C W Figure...

Page 23: ...n Single Clock Mode to Data Valid 0 45 0 45 0 50 ns tDOH tCHQX Data Output Hold after Output C C Clock Rise Active to Active 0 45 0 45 0 50 ns tCCQO tCHCQV C C Clock Rise to Echo Clock Valid 0 45 0 45...

Page 24: ...D50 D51 D61 D31 D11 D10 D60 Q C C DON T CARE UNDEFINED t CQ CQ tKHCH tCO tKHCH tCLZ CHZ tKH tKL Q00 Q01 Q20 tKHKH tCYC Q21 Q40 Q41 tCQD tDOH tCCQO tCQOH tCCQO tCQOH tCQDOH Notes 26 Q00 refers to outp...

Page 25: ...Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C1910BV18 250BZI CY7C1312BV18 250BZI CY7C1314BV18 250BZI CY7C1310BV18 250BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb...

Page 26: ...8 167BZXC CY7C1310BV18 167BZI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C1910BV18 167BZI CY7C1312BV18 167BZI CY7C1314BV18 167BZI CY7C1310BV18 167BZXI 51 85180 165 Bal...

Page 27: ...0 05 M C B A 0 15 4X 0 35 0 06 SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H J K L M N 11 11 10 9 8 6 7 5 4 3 2 1 P R P R K M N L...

Page 28: ...page 18 Replaced Three state with Tri state Changed the description of IX from Input Load Current to Input Leakage Current on page 13 Modified the IDD and ISB values Modified test condition in Footno...

Page 29: ...thout the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF...

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