CY7C1310BV18, CY7C1910BV18
CY7C1312BV18, CY7C1314BV18
Document #: 38-05619 Rev. *F
Page 23 of 29
Switching Characteristics
Over the Operating Range
[20, 21]
Cypress
Parameter
Consortium
Parameter
Description
250 MHz
200 MHz
167 MHz
Unit
Min
Max
Min
Max
Min
Max
t
POWER
V
DD
(Typical) to the First Access
[22]
1
1
1
ms
t
CYC
t
KHKH
K Clock and C Clock Cycle Time
4.0
8.4
5.0
8.4
6.0
8.4
ns
t
KH
t
KHKL
Input Clock (K/K and C/C) HIGH
1.6
–
2.0
–
2.4
–
ns
t
KL
t
KLKH
Input Clock (K/K and C/C) LOW
1.6
–
2.0
–
2.4
–
ns
t
KHKH
t
KHKH
K Clock Rise to K Clock Rise and C to C Rise
(rising edge to rising edge)
1.8
–
2.2
–
2.7
–
ns
t
KHCH
t
KHCH
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge)
0
1.8
0
2.2
0
2.7
ns
Setup Times
t
SA
t
AVKH
Address Setup to K Clock Rise
0.35
–
0.4
–
0.5
–
ns
t
SC
t
IVKH
Control Setup to K Clock Rise (RPS, WPS)
0.35
–
0.4
–
0.5
–
ns
t
SCDDR
t
IVKH
DDR Control Setup to Clock (K/K) Rise
(BWS
0
, BWS
1
, BWS
3
, BWS
4
)
0.35
–
0.4
–
0.5
–
ns
t
SD
[23]
t
DVKH
D
[X:0]
Setup to Clock (K/K) Rise
0.35
–
0.4
–
0.5
–
ns
Hold Times
t
HA
t
KHAX
Address Hold after K Clock Rise
0.35
–
0.4
–
0.5
–
ns
t
HC
t
KHIX
Control Hold after K Clock Rise (RPS, WPS)
0.35
–
0.4
–
0.5
–
ns
t
HCDDR
t
KHIX
DDR Control Hold after Clock (K/K) Rise
(BWS
0
, BWS
1
, BWS
3
, BWS
4
)
0.35
–
0.4
–
0.5
–
ns
t
HD
t
KHDX
D
[X:0]
Hold after Clock (K/K) Rise
0.35
–
0.4
–
0.5
–
ns
Output Times
t
CO
t
CHQV
C/C Clock Rise (or K/K in Single Clock Mode) to Data Valid
–
0.45
–
0.45
–
0.50
ns
t
DOH
t
CHQX
Data Output Hold after Output C/C Clock Rise
(Active to Active)
–0.45
–
–0.45
–
–0.50
–
ns
t
CCQO
t
CHCQV
C/C Clock Rise to Echo Clock Valid
–
0.45
–
0.45
–
0.50
ns
t
CQOH
t
CHCQX
Echo Clock Hold after C/C Clock Rise
–0.45
–
–0.45
–
–0.50
–
ns
t
CQD
t
CQHQV
Echo Clock High to Data Valid
–
0.30
–
0.35
–
0.40
ns
t
CQDOH
t
CQHQX
Echo Clock High to Data Invalid
–0.30
–
–0.35
–
–0.40
–
ns
t
CHZ
t
CHQZ
Clock (C/C) Rise to High-Z (Active to High-Z)
[24, 25]
–
0.45
–
0.45
–
0.50
ns
t
CLZ
t
CHQX1
Clock (C/C) Rise to Low-Z
[24, 25]
–0.45
–
–0.45
–
–0.50
–
ns
DLL Timing
t
KC Var
t
KC Var
Clock Phase Jitter
–
0.20
–
0.20
–
0.20
ns
t
KC lock
t
KC lock
DLL Lock Time (K, C)
1024
–
1024
–
1024
–
Cycles
t
KC Reset
t
KC Reset
K Static to DLL Reset
30
–
30
–
30
–
ns
Notes
21. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timing of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
22. This part has a voltage regulator internally; t
POWER
is the time that the power is supplied above V
DD
minimum initially before a read or write operation is initiated.
23. For D2 data signal on CY7C1910BV18 device, t
SD
is 0.5 ns for 200 MHz, and 250 MHz frequencies.
24. t
CHZ
, t
CLZ
, are specified with a load capacitance of 5 pF as in part (b) of
AC Test Loads and Waveforms
. Transition is measured ±100 mV from steady state voltage.
25. At any voltage and temperature t
CHZ
is less than t
CLZ
and t
CHZ
less than t
CO
.
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