Cypress Semiconductor CY7C1310AV18 Specification Sheet Download Page 20

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CY7C1310AV18

CY7C1312AV18

CY7C1314AV18

PRELIMINARY

Document #: 38-05497 Rev. *A

Page 20 of 21

QDR



SRAMs and Quad Data Rate



SRAMs comprise a new family of products developed by Cypress, Hitachi, IDT, NEC and

Samsung technology. All product and company names mentioned in this document are the trademarks of their respective holders.

Ordering Information

Speed

(MHz)

Ordering Code

Package

Name

Package Type

Operating

Range

167

CY7C1310AV18-167BZC

BB165D

13 x 15 x 1.4 mm FBGA

Commercial

CY7C1312AV18-167BZC
CY7C1314AV18-167BZC

133

CY7C1310AV18-133BZC

BB165D

13 x 15 x 1.4 mm FBGA

Commercial

CY7C1312AV18-133BZC
CY7C1314AV18-133BZC

Package Diagram

51-85180-**

165 FBGA 13 x 15 x 1.40 mm BB165D

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Summary of Contents for CY7C1310AV18

Page 1: ...ead operations and the Write Port has dedicated Data Inputs to support Write opera tions QDR II architecture has separate data inputs and data outputs to completely eliminate the need to turn around t...

Page 2: ...ata Reg RPS WPS Q 17 0 Control Logic Address Register Reg Reg Reg 18 19 18 36 18 BWS 1 0 VREF Write Add Decode 18 A 18 0 19 C C 18 512K x 18 Array 512K x 18 Array Write Reg Write Reg CQ CQ 18 DOFF Log...

Page 3: ...VREF NC NC VDDQ NC VDDQ NC NC VDDQ VDDQ VDDQ D1 VDDQ NC Q1 NC VDDQ VDDQ NC VSS NC D0 NC TDI TMS VSS A NC A NC D2 NC ZQ NC Q0 NC NC NC NC A CY7C1312AV18 1M 18 11 15 BGA 2 3 4 5 6 7 1 A B C D E F G H J...

Page 4: ...tten into the device A Input Synchronous Address Inputs Sampled on the rising edge of the K read address and K write address clocks during active read and write operations These address inputs are mul...

Page 5: ...to drive out data through Q x 0 when in single clock mode CQ Echo Clock CQ is referenced with respect to C This is a free running clock and is synchronized to the output clock C of the QDR II In the s...

Page 6: ...on of wait states in a depth expanded memory Write Operations Write operations are initiated by asserting WPS active at the rising edge of the Positive Input Clock K On the same K clock rise the data...

Page 7: ...et by slowing the cycle time of input clocks K and K to greater than 30 ns Application Example 1 Truth Table 2 3 4 5 6 7 Operation K RPS WPS DQ DQ Write Cycle Load address on the rising edge of K cloc...

Page 8: ...es during this portion of a write operation H H L H No data is written into the devices during this portion of a write operation Write Cycle Descriptions CY7C1314AV18 2 8 BWS0 BWS1 BWS2 BWS3 K K Comme...

Page 9: ...t LOW Voltage 12 13 0 3 VREF 0 1 V VIN Clock Input Voltage 0 3 VDDQ 0 3 V IX Input Load Current GND VI VDDQ 5 5 A IOZ Output Leakage Current GND VI VDDQ Output Disabled 5 5 A VREF InputReferenceVoltag...

Page 10: ...tCQOH tCHCQX Echo Clock Hold after C C Clock Rise 0 50 0 50 ns tCQD tCQHQV Echo Clock High to Data Valid 0 40 0 40 ns tCQDOH tCQHQX Echo Clock High to Data Invalid 0 40 0 40 ns tCHZ tCHZ Clock C and C...

Page 11: ...CCLK Clock Input Capacitance 6 pF CO Output Capacitance 7 pF AC Test Loads and Waveforms Note 20 Tested initially and after any design or process change that may affect these parameters 1 25V 0 25V R...

Page 12: ...if address A2 A1 then data Q20 D10 and Q21 D11 Write data is forwarded immediately as read results This note applies to the whole diagram Read Write Deselect Sequence K 1 2 3 4 5 8 10 6 7 K RPS WPS A...

Page 13: ...is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruct...

Page 14: ...ter between the TDI and TDO pins PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells pri or to the selection of another boundary sca...

Page 15: ...ents the value at TMS at the rising edge of TCK TAP Controller State Diagram 24 TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR SELECT IR SCAN...

Page 16: ...tage IOL 2 0 mA 0 4 V VOL2 Output LOW Voltage IOL 100 A 0 2 V VIH Input HIGH Voltage 0 65VDD VDD 0 3 V VIL Input LOW Voltage 0 3 0 35VDD V IX Input and OutputLoad Current GND VI VDD 5 5 A Note 25 Thes...

Page 17: ...imes tTMSH TMS Hold after TCK Clock Rise 10 ns tTDIH TDI Hold after Clock Rise 10 ns tCH Capture Hold after Clock Rise 10 ns Output Times tTDOV TCK Clock LOW to TDO Valid 20 ns tTDOX TCK Clock LOW to...

Page 18: ...dor ID code and places the register between TDI and TDO This operation does not affect SRAM operation SAMPLE Z 010 Captures the Input Output contents Places the boundary scan register between TDI and...

Page 19: ...1 6C 52 8A 53 7A 54 7B 55 6B 56 6A 57 5B 58 5A 59 4A 60 5C 61 4B 62 3A 63 1H 64 1A 65 2B 66 3B 67 1C 68 1B 69 3D 70 3C 71 1D 72 2C 73 3E Boundary Scan Order continued Bit Bump ID 74 2D 75 2E 76 1E 77...

Page 20: ...names mentioned in this document are the trademarks of their respective holders Ordering Information Speed MHz Ordering Code Package Name Package Type Operating Range 167 CY7C1310AV18 167BZC BB165D 13...

Page 21: ...nt History Page Document Title CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 18 Mb QDR II SRAM 2 Word Burst Architecture Document Number 38 05497 REV ECN No Issue Date Orig of Change Description of Change 20...

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