CY62157ESL MoBL
®
8-Mbit (512K x 16) Static RAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 001-43141 Rev. **
Revised January 04, 2008
Features
■
Very high speed: 45 ns
■
Wide voltage range: 2.2V–3.6V and 4.5V–5.5V
■
Ultra low standby power
❐
Typical Standby current: 2
μ
A
❐
Maximum Standby current: 8
μ
A
■
Ultra low active power
❐
Typical active current: 1.8 mA at f = 1 MHz
■
Easy memory expansion with CE and OE features
■
Automatic power down when deselected
■
CMOS for optimum speed and power
■
Available in Pb-free 44-pin TSOP II package
Functional Description
The CY62157ESL is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life
™
(MoBL
®
) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Place the device
into standby mode when deselected (CE HIGH or both BHE and
BLE are HIGH). The input or output pins (IO
0
through IO
15
) are
placed in a high impedance state when:
■
Deselected (CE
HIGH)
■
Outputs are disabled (OE HIGH)
■
Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■
Write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO
0
through IO
7
) is written into the location
specified on the address pins (A
0
through A
18
). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO
8
through IO
15
)
is written into the location specified on the address pins (A
0
through A
18
).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO
0
to IO
7
. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO
8
to IO
15
. See the
Truth Table on page 10
for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note
AN1064, SRAM System Guidelines
.
Logic Block Diagram
512K x 16
RAM Array
IO
0
–IO
7
ROW DE
COD
E
R
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
SE
NS
E A
M
P
S
DATA IN DRIVERS
OE
A
4
A
3
IO
8
–IO
15
WE
BLE
BHE
A
16
A
0
A
1
A
17
A
9
A
10
A
18
CE
Power Down
Circuit
BHE
BLE
CE
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