CY14B101K
Document Number: 001-06401 Rev. *I
Page 4 of 28
SRAM READ and WRITE operations that are in progress when
HSB is driven LOW by any means are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
the CY14B101K continues SRAM operations for t
DELAY
. During
t
DELAY
, multiple SRAM READ operations take place. If a WRITE
is in progress when HSB is pulled LOW, it is allowed a time,
t
DELAY
, to complete. However, any SRAM WRITE cycles
requested after HSB goes LOW are inhibited until HSB returns
HIGH.
During any STORE operation, regardless of how it is initiated,
the CY14B101K continues to drive the HSB pin LOW, releasing
it only when the STORE is complete. After completing the
STORE operation, the CY14B101K remains disabled until the
HSB pin returns HIGH. Leave the HSB unconnected if it is not
used.
Hardware RECALL (Power Up)
During power up or after any low power condition
(V
CC
< V
SWITCH
), an internal RECALL request is latched. When
V
CC
again exceeds the sense voltage of V
SWITCH
, a RECALL
cycle automatically initiates and takes t
HRECALL
to complete.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14B101K software
STORE cycle is initiated by executing sequential CE controlled
READ cycles from six specific address locations in exact order.
During the STORE cycle, an erase of the previous nonvolatile
data is first performed followed by a program of the nonvolatile
elements. After a STORE cycle is initiated, further READs and
WRITEs are inhibited until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If it intervenes, the
sequence is aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ
sequence are performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE cycle
The software sequence is clocked with CE controlled READs or
OE controlled READs. After the sixth address in the sequence is
entered, the STORE cycle commences and the chip is disabled.
It is important to use read cycles and not write cycles in the
sequence, although it is not necessary that OE be LOW for a
valid sequence. After the t
STORE
cycle time is fulfilled, the SRAM
is activated again for READ and WRITE operation.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled READ operations are
performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared and then the nonvolatile information is transferred into
the SRAM cells. After the t
RECALL
cycle time, the SRAM is again
ready for READ and WRITE operations. The RECALL operation
does not alter the data in the nonvolatile elements.
Data Protection
The CY14B101K protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when V
CC
is less than V
SWITCH
. If the CY14B101K is in a WRITE
mode (both CE and WE LOW) at power up, after a RECALL or
after a STORE, the WRITE is inhibited until a negative transition
on CE or WE is detected. This protects against inadvertent writes
during power up or brownout conditions.
Noise Considerations
The CY14B101K is a high speed memory and must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between V
CC
and V
SS
, using leads and traces that are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
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