Cypress Semiconductor CY14B101K, Specification Sheet

Page: 20 / 28

CY14B101K
Document Number: 001-06401 Rev. *I Page 20 of 28
Software Controlled STORE/RECALL Cycles
[21, 22]
Parameter
Alt.
Parameter
Description
25 ns 35 ns 45 ns
Unit
Min Max Min Max Min Max
t
RC
t
AVAV
STORE/RECALL Initiation Cycle
Time 25 35 45 ns
t
SA
t
AVEL
Address Setup Time 0 0 0 ns
t
CW
t
ELEH
Clock Pulse Width 20 25 30 ns
t
HA
t
EHAX
Address Hold Time 1 1 1 ns
t
RECALL
RECALL Duration 170 170 170
μ
s
Figure 13. CE Controlled Software STORE/RECALL Cycle
[22]
Figure 14. OE Controlled Software STORE/RECALL Cycle
[22]
t
RC
t
RC
t
SA
t
SCE
t
HA
t
STORE
/ t
RECALL
DATA VALID DATA VALID
6 # S S E R D D A 1 # S S E R D D A
HIGH IMPEDANCE
ADDRESS
CE
OE
DQ (DATA)
t
RC
t
RC
6 # S S E R D D A 1 # S S E R D D A
ADDRESS
t
SA
t
SCE
t
HA
t
STORE
/ t
RECALL
DATA VALID DATA VALID
HIGH IMPEDANCE
CE
OE
DQ (DATA)
Notes
21. The software sequence is clocked with CE controlled or OE controlled READs.
22. The six consecutive addresses are read in the order listed in the
Table 2 on page 6. WE is HIGH during all six consecutive cycles.
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